LTC3208 Datasheet, PDF (18/24 Pages) Linear Technology – High Current Software Confi gurable Multidisplay LED Controller

LTC3208
APPLICATIO S I FOR ATIO
the rated voltage is applied. Therefore, when comparing
different capacitors, it is often more appropriate to compare
the amount of achievable capacitance for a given case size
rather than comparing the specified capacitance value. For
example, overrated voltage and temperature conditions, a
1µF, 10V, Y5V ceramic capacitor in a 0603 case may not
provide any more capacitance than a 0.22µF, 10V, X7R
available in the same case. The capacitor manufacturer’s
data sheet should be consulted to determine what value
of capacitor is needed to ensure minimum capacitances
at all temperatures and voltages.
Table 1 shows a list of ceramic capacitor manufacturers
and how to contact them:
Table 1. Recommended Capacitor Vendors
AVX
Kemet
Murata
Taiyo Yuden
Vishay
www.avxcorp.com
www.kemet.com
www.murata.com
www.t-yuden.com
www.vishay.com
Layout Considerations and Noise
Due to its high switching frequency and the transient
currents produced by the LTC3208, careful board layout
is necessary. A true ground plane and short connections
to all capacitors will improve performance and ensure
proper regulation under all conditions.
The flying capacitor pins C1P, C2P, C1M and C2M will have
very high edge rate waveforms. The large dv/dt on these
pins can couple energy capacitively to adjacent PCB runs.
Magnetic fields can also be generated if the flying capacitors
are not close to the LTC3208 (i.e., the loop area is large).
To decouple capacitive energy transfer, a Faraday shield
may be used. This is a grounded PCB trace between the
sensitive node and the LTC3208 pins. For a high quality
AC ground, it should be returned to a solid ground plane
that extends all the way to the LTC3208.
The following guidelines should be followed when design-
ing a PCB layout for the LTC3208.
• The exposed pad should be soldered to a large copper
plane that is connected to a solid, low impedance ground
plane using plated, through-hole vias for proper heat
sinking and noise protection.
• Input and output capacitors (C1 and C4) must be placed
close to the part.
• The flying capacitors (C2 and C3) must be placed close
to the part. The traces running from the pins to the
capacitor pads should be as wide as possible.
• V_BAT, CPO traces must be made wide to minimize
inductance and handle the high currents.
• LED pads must be large and connected to other layers
of metal to ensure proper heat sinking.
GND PLANE
LAYER
CPO
GND
GND
C4
V_BAT PLANE
LAYER
1
CONNECT TO
GND PLANE LAYER
C2
ALL VIAS LABELED GND
ARE CONNECTED TO
GND PLANE LAYER
C3
V_BAT
ALL VIAS LABELED V_BAT
ARE CONNECTED TO
V_BAT PLANE LAYER
GND
C1
V_BAT
GND
V_BAT PLANE
LAYER
V_BAT
C5
R1
C6
GND
R_REF
DV_CC GND PLANE
GND
GND
LAYER
3208 F07
Figure 7. PC Board Layout Example
3208fa
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