LTC3208 Datasheet, PDF (16/24 Pages) Linear Technology – High Current Software Confi gurable Multidisplay LED Controller

LTC3208
U
OPERATIO
Bus Speed
The I²C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I²C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
START and STOP Conditions
A bus-master signals the beginning of a communication
to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA
from high to low while SCL is high. When the master has
finished communicating with the slave, it issues a STOP
condition by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I²C device.
Byte Format
Each byte sent to the LTC3208 must be 8 bits long fol-
lowed by an extra clock cycle for the Acknowledge bit to
be returned by the LTC3208. The data should be sent to
the LTC3208 most significant bit (MSB) first.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave (LTC3208) lets the master know
that the latest byte of information was received. The
Acknowledge related clock pulse is generated by the
master. The master releases the SDA line (HIGH) during
the Acknowledge clock cycle. The slave-receiver must pull
down the SDA line during the Acknowledge clock pulse
so that it remains a stable LOW during the HIGH period
of this clock pulse.
Slave Address
The LTC3208 responds to only one 7-bit address which
has been factory programmed to 0011011. The eighth bit
of the address byte (R/W) must be 0 for the LTC3208 to
recognize the address since it is a write only device. This
effectively forces the address to be 8 bits long where the
least significant bit of the address is 0. If the correct seven
bit address is given but the R/W bit is 1, the LTC3208 will
not respond.
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Bus Write Operation
The master initiates communication with the LTC3208
with a START condition and a 7-bit address followed by
the Write Bit R/W = 0. If the address matches that of the
LTC3208, the LTC3208 returns an Acknowledge. The mas-
ter should then deliver the most significant sub-address
byte for the data register to be written. Again the LTC3208
acknowledges and then the data is delivered starting with
the most significant bit. This cycle is repeated until all of the
required data registers have been written. Any number of
data latches can be written. Each data byte is transferred to
an internal holding latch upon the return of an Acknowledge.
After all data bytes have been transferred to the LTC3208,
the master may terminate the communication with a STOP
condition. Alternatively, a REPEAT-START condition can be
initiated by the master and another chip on the I²C bus can
be addressed. This cycle can continue indefinitely and the
LTC3208 will remember the last input of valid data that it
received. Once all chips on the bus have been addressed
and sent valid data, a global STOP condition can be sent
and the LTC3208 will update all registers with the data
that it had received.
In certain circumstances the data on the I²C bus may
become corrupted. In these cases the LTC3208 responds
appropriately by preserving only the last set of complete
data that it has received. For example, assume the LTC3208
has been successfully addressed and is receiving data
when a STOP condition mistakenly occurs. The LTC3208
will ignore this stop condition and will not respond until a
new START condition, correct address, sub-address and
new set of data and STOP condition are transmitted.
Likewise, if the LTC3208 was previously addressed and
sent valid data but not updated with a STOP, it will respond
to any STOP that appears on the bus with only one ex-
ception, independent of the number of REPEAT-START’s
that have occurred. If a REPEAT-START is given and the
LTC3208 successfully acknowledges its address, it will
not respond to a STOP until all bytes of the new data have
been received and acknowledged.
Shared data registers will have all 8 bits rewritten since a
common acknowledge signal writes these registers. The
shared registers include REGA, REGB and REGF.
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