LTC2410_15 Datasheet, PDF (18/48 Pages) Linear Technology – 24-Bit No Latency ADC with Differential Input and Differential Reference

LTC2410
APPLICATIO S I FOR ATIO
2.7V TO 5.5V
1µF
2
V_CC
14
F_O
REFERENCE
VOLTAGE
0.1V TO V_CC
LTC2410
3 _REF+
4 _REF–
SCK ¹³
ANALOG INPUT RANGE ⁵ _IN+
–0.5V_REF TO 0.5V_{REF 6 IN–}
1, 7, 8, 9, 10, 15, 16
GND
12
SDO
11
CS
V_{CC= 50Hz REJECTION}
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
3-WIRE
SPI INTERFACE
CS
BIT 0
TEST EOC TEST EOC
BIT 31 BIT 30
BIT 29 BIT 28 BIT 27
BIT 9 BIT 8
SDO
EOC
EOC
Hi-Z
Hi-Z
Hi-Z
SIG
MSB
SCK
(EXTERNAL)
SLEEP
CONVERSION
DATA OUTPUT
SLEEP
DATA OUTPUT
Figure 6. External Serial Clock, Reduced Data Output Length
TEST EOC
Hi-Z
CONVERSION
2410 F06
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC␣ =␣ 0 once the conversion enters the low power sleep
state. On the falling edge of EOC, the conversion result is
loaded into an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK.
Data is shifted out the SDO pin on each falling edge of SCK
enabling external circuitry to latch data on the rising edge
of SCK. EOC can be latched on the first rising edge of SCK.
On the 32nd falling edge of SCK, SDO goes HIGH (EOC␣ =␣ 1)
indicating a new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
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enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t_EOCtest after the falling edge of CS
(if EOC = 0) or t_EOCtest after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t_EOCtest is 23µs
if the device is using its internal oscillator (F₀ = logic LOW
or HIGH). If F_O is driven by an external oscillator of