LTC4006_15 Datasheet, PDF (17/20 Pages) Linear Technology – 4A, High Efficiency, Standalone Li-Ion Battery Charger

LTC4006
APPLICATIO S I FOR ATIO
V_IN
Q1A
100k
TGATE
ZENER
18V
INDUCTOR R_SENSE
V_OUT
Q1B
V_BAT
4006 F12
Figure 12. Optional Simple High
Efficiency Battery Discharge Path
0V keeping Q1B in the off state while P-channel MOSFET
Q1A is on. If V_IN were to suddenly go away, Q1B internal
diode will provide a passive but instant discharge path for
battery current to reach V_OUT and hold up the load. Q1B
internal diode has the same current rating as the FET itself,
but has a very high V_f of about a volt such that heat will
quickly build up in Q1B if left alone. However as V_IN’s voltage
falls below V_BAT by Q1B’s V_GS threshold, Q1B will then turn
on shorting out its internal diode removing both the heat
and voltage losses created by the diode. When V_IN falls to
zero volts, Q1B gate will be driven to the same voltage as
V_BAT providing the lowest possible RDS_ON value. A zener
diode along with a 100k resistor in series with the Q1B gate
protects the gate from any hazardous voltage spikes that
can exceed Q1B maximum permissible V_GS voltage. The
zener voltage rating must be less than Q1B V_GS(MAX) volt-
age but greater than V_BAT.
Since Q1A and Q1B are always at opposite states and share
the same load, it is often advantagous to combine both FETs
into a single package and save PCB space. The P_D rate of
the FET that is on is enhanced when the other FET is off. The
choice of a combined Q1 should take into account the high-
est load current conditions of both paths and choose
whichever is greater as the driving force behind the MOSFET
selection. If the V_IN supply is going to collapse very slowly
such that Q1B is not turned on quickly enough for the given
load and stay within its P_D limits, you should install a suit-
able Schottky diode in parallel with Q1B.
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall times
should be minimized. To prevent magnetic and electrical
field radiation and high frequency resonant problems,
proper layout of the components connected to the IC is
essential. (See Figure 13.) Here is a PCB layout priority list
for proper layout. Layout the PCB using this specific order.
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that con-
nect to the switching FET source pins. The IC can be
placed on the opposite side of the PCB relative to above.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
SWITCH NODE
HIGH
V_IN
C2
FREQUENCY
CIRCULATING
PATH
L1
V_BAT
D1
C3
BAT
4006 F13
Figure 13. High Speed Switching Path
4006fa
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