LTC3609 Datasheet, PDF (17/24 Pages) Linear Technology – 32V, 6A Monolithic Synchronous Step-Down DC/DC Converter

LTC3609
APPLICATIONS INFORMATION
4. C_IN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I²R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including C_OUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to ΔI_LOAD (ESR), where ESR is the effective series
resistance of C_OUT. ΔI_LOAD also begins to charge or dis-
charge C_OUT generating a feedback error signal used by the
regulator to return V_OUT to its steady-state value. During
this recovery time, V_OUT can be monitored for overshoot
or ringing that would indicate a stability problem. The I_TH
pin external components shown in Figure 6 will provide
adequate compensation for most applications. For a
detailed explanation of switching control loop theory see
Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: V_IN = 5V to 32V (12V nominal), V_OUT =
2.5V ± 5%, I_OUT(MAX) = 6A, f = 550kHz. First, calculate the
timing resistor with V_ON = V_OUT:
R_ON
=
(2.4V
2.5V
)(550kHz
)(10pF)
=
187k
and choose the inductor for about 40% ripple current at
the maximum V_IN:
L
=
2.5V
(550kHz)(0.4)(6A)
⎛
⎝⎜
1−
2.5V
32V
⎞
⎠⎟
=
1.8µH
Selecting a standard value of 1.5μH results in a maximum
ripple current of:
ΔI_L
=
2.5V
(550kHz)(1.5μH)
⎛
⎝⎜
1–
2.5V
12V
⎞
⎠⎟
=
2.4A
Next, set up V_RNG voltage and check the I_LIMIT. Tying V_RNG
to GND will set the typical current limit to 9A, and tying
V_RNG to 1.2V will result in a typical current around 14A.
C_IN is chosen for an RMS current rating of about 5A at
85°C. The ceramic output capacitors are chosen for an
ESR of 0.002Ω to minimize output voltage changes due
to inductor ripple current and load steps. The ripple volt-
age is:
ΔV_OUT(RIPPLE) = ΔI_L(MAX) (ESR)
= (2.4A) (0.002Ω) = 4.8mV
and a 0A to 6A load step will only cause an output
change of:
ΔV_OUT(STEP) = ΔI_LOAD (ESR) = (6A) (0.002Ω) = 12mV
An optional 22μF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 6.
PC Board Layout Checklist
When laying out a PC board follow one of the two sug-
gested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents, a
multilayer board is recommended to help with heat sinking
of power components.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with the
LTC3609.
• Place C_IN and C_OUT all in one compact area, close to
the LTC3609. It may help to have some components
on the bottom side of the board.
• Keep small-signal components close to the LTC3609.
• Ground connections (including LTC3609 SGND and
PGND) should be made through immediate vias to
the ground plane. Use several larger vias for power
components.
3609f
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