LTC3604 Datasheet, PDF (17/24 Pages) Linear Technology – 2.5A, 15V Monolithic Synchronous Step-Down Regulator

LTC3604
APPLICATIONS INFORMATION
Figure 5 is a temperature derating curve based on the
DC1353A demo board. It can be used to estimate the
maximum allowable ambient temperature for given DC
load currents in order to avoid exceeding the maximum
operating junction temperature of 125°C.
3.0
V_IN = 12V
V_OUT = 1.8V
2.5
f_O = 1MHz
DC1353A
2.0
1.5
1.0
0.5
0
25
50
75
100
125
TEMPERATURE (°C)
3604 F05
Figure 5. Load Current vs Ambient Temperature
Junction Temperature Measurement
The junction-to-ambient thermal resistance will vary de-
pending on the size and amount of heat sinking copper on
the PCB board where the part is mounted, as well as the
amount of air flow on the device. One of the ways to mea-
sure the junction temperature directly is to use the internal
junction diode on one of the pins (PGOOD) to measure
its diode voltage change based on ambient temperature
change. First remove any external passive component on
the PGOOD pin, then pull out 100μA from the PGOOD pin
to turn on its internal junction diode and bias the PGOOD
pin to a negative voltage. With no output current load,
measure the PGOOD voltage at an ambient temperature
of 25°C, 75°C and 125°C to establish a slope relationship
between the delta voltage on PGOOD and delta ambient
temperature. Once this slope is established, then the junc-
tion temperature rise can be measured as a function of
power loss in the package with corresponding output load
current. Keep in mind that doing so will violate absolute
maximum voltage ratings on the PGOOD pin, however,
with the limited current, no damage will result.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3604.
1. Do the capacitors C_IN connect to V_IN and PGND as close
to the pins as possible? These capacitors provide the AC
current to the internal power MOSFETs and drivers. The
(–) plate of C_IN should be closely connected to PGND
and the (–) plate of C_OUT.
2. The output capacitor, C_OUT, and inductor L1 should
be closely connected to minimize loss. The (–) plate
of C_OUT should be closely connected to PGND and the
(–) plate of C_IN.
3. The resistive divider, R1 and R2, must be connected
between the (+) plate of C_OUT and a ground line termi-
nated near SGND. The feedback signal, V_FB, should be
routed away from noisy components and traces such as
the SW line, and its trace length should be minimized.
In addition, RT and the loop compensation components
should be terminated to SGND.
4. Keep sensitive components away from the SW pin. The
R_RT resistor, the feedback resistors, the compensation
components, and the INTV_CC bypass capacitor should all
be routed away from the SW trace and the inductor.
5. A ground plane is preferred, but if not available the
signal and power grounds should be segregated with
both connecting to a common, low noise reference
point. The point at which the ground terminals of the
V_IN and V_OUT bypass capacitors are connected makes a
good, low noise reference point. The connection to the
PGND pin should be made with a minimal resistance
trace from the reference point.
6. Flood all unused areas on all layers with copper in order
to reduce the temperature rise of power components.
These copper areas should be connected to the exposed
backside connection of the IC.
3604f
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