LTC2172-12_15 Datasheet, PDF (17/34 Pages) Linear Technology – 12-Bit, 65Msps/40Msps/ 25Msps Low Power Quad ADCs

LTC2172-12/
LTC2171-12/LTC2170-12
Pin Functions
A_IN1+ (Pin 1): Channel 1 Positive Differential Analog
Input.
A_IN1– (Pin 2): Channel 1 Negative Differential Analog
Input.
V_CM12 (Pin 3): Common Mode Bias Output, Nominally
Equal to V_DD/2. V_CM should be used to bias the common
mode of the analog inputs of channels 1 and 2. Bypass
to ground with a 0.1µF ceramic capacitor.
A_IN2+ (Pin 4): Channel 2 Positive Differential Analog
Input.
A_IN2– (Pin 5): Channel 2 Negative Differential Analog
Input.
REFH (Pins 6, 7): ADC High Reference. Bypass to Pin 8
and Pin 9 with a 2.2µF ceramic capacitor, and to ground
with a 0.1µF ceramic capacitor.
REFL (Pins 8, 9): ADC Low Reference. Bypass to Pin 6
and Pin 7 with a 2.2µF ceramic capacitor, and to ground
with a 0.1µF ceramic capacitor.
A_IN3+ (Pin 10): Channel 3 Positive Differential Analog
Input.
A_IN3– (Pin 11): Channel 3 Negative Differential Analog
Input.
V_CM34 (Pin 12): Common Mode Bias Output, Nominally
Equal to V_DD/2. V_CM should be used to bias the common
mode of the analog inputs of channels 3 and 4. Bypass
to ground with a 0.1µF ceramic capacitor.
A_IN4+ (Pin 13): Channel 4 Positive Differential Analog
Input.
A_IN4– (Pin 14): Channel 4 Negative Differential Analog
Input.
V_DD (Pins 15, 16, 51, 52): Analog Power Supply, 1.7V
to 1.9V. Bypass to ground with 0.1µF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
ENC⁺ (Pin 17): Encode Input. Conversion starts on the
rising edge.
ENC^– (Pin 18): Encode Complement Input. Conversion
starts on the falling edge.
CS (Pin 19): In serial programming mode (PAR/SER = 0V),
CS is the serial interface chip select input. When CS is low,
SCK is enabled for shifting data on SDI into the mode
control registers. In parallel programming mode (PAR/SER
= V_DD), CS selects two-lane or one-lane output mode. CS
can be driven with 1.8V to 3.3V logic.
SCK (Pin 20): In serial programming mode (PAR/SER
= 0V), SCK is the serial interface clock input. In parallel
programming mode (PAR/SER = V_DD), SCK selects 3.5mA
or 1.75mA LVDS output currents. SCK can be driven with
1.8V to 3.3V logic.
SDI (Pin 21): In serial programming mode (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In parallel programming mode (PAR/SER =
V_DD), SDI can be used to power down the part. SDI can
be driven with 1.8V to 3.3V logic.
GND (Pins 22, 45, 49, Exposed Pad Pin 53): ADC Power
Ground. The exposed pad must be soldered to the PCB
ground.
OGND (Pin 33): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
OV_DD (Pin 34): Output Driver Supply, 1.7V to 1.9V. Bypass
to ground with a 0.1µF ceramic capacitor.
SDO (Pin 46): In serial programming mode (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control reg-
isters and can be latched on the falling edge of SCK.
SDO is an open-drain N-channel MOSFET output that
requires an external 2k pull-up resistor of 1.8V to
3.3V. If readback from the mode control registers is
not needed, the pull-up resistor is not necessary and
SDO can be left unconnected. In parallel programming
mode (PAR/SER = V_DD), SDO is an input that enables
internal 100Ω termination resistors on the digital
outputs. When used as an input, SDO can be driven
with 1.8V to 3.3V logic through a 1k series resistor.
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