LTC2172-12_15 Datasheet, PDF (1/34 Pages) Linear Technology – 12-Bit, 65Msps/40Msps/ 25Msps Low Power Quad ADCs

LTC2172-12/
LTC2171-12/LTC2170-12
12-Bit, 65Msps/40Msps/
25Msps Low Power Quad ADCs
Features
Description
n _{4-Channel Simultaneous Sampling ADC}
n _{71dB SNR}
n _{90dB SFDR}
n _{Low Power: 306mW/198mW/160mW Total,}
77mW/50mW/40mW per Channel
n _{Single 1.8V Supply}
n _{Serial LVDS Outputs: One or Two Bits per Channel}
n _{Selectable Input Ranges: 1VP-P to 2VP-P}
n _{800MHz Full Power Bandwidth Sample-and-Hold}
n _{Shutdown and Nap Modes}
n _{Serial SPI Port for Configuration}
n _{Pin-Compatible 14-Bit and 12-Bit Versions}
n _{52-Pin (7mm × 8mm) QFN Package}
Applications
n _{Communications}
n _{Cellular Base Stations}
n _{Software Defined Radios}
n _{Portable Medical Imaging}
n _{Multichannel Data Acquisition}
n _{Nondestructive Testing}
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
The LTC^®2172-12/LTC2171-12/LTC2170-12 are 4-channel,
simultaneous sampling 12-bit A/D converters designed for
digitizing high frequency, wide dynamic range signals. They
are perfect for demanding communications applications
with AC performance that includes 71dB SNR and 90dB
spurious free dynamic range (SFDR). An ultralow jitter of
0.15ps_RMS allows undersampling of IF frequencies with
excellent noise performance.
DC specifications include ±0.3LSB INL (typ), ±0.1LSB
DNL (typ) and no missing codes over temperature. The
transition noise is a low 0.3LSB_RMS.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode) or one bit at a time (1-lane mode). The LVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
The ENC⁺ and ENC^– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
Typical Application
CHANNEL 1
ANALOG
S/H
INPUT
1.8V
V_DD
12-BIT
ADC CORE
1.8V
OV_DD
CHANNEL 2
ANALOG
S/H
INPUT
CHANNEL 3
ANALOG
S/H
INPUT
12-BIT
ADC CORE
12-BIT
ADC CORE
DATA
SERIALIZER
CHANNEL 4
ANALOG
S/H
INPUT
12-BIT
ADC CORE
ENCODE
INPUT
PLL
GND
OGND
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
DATA
CLOCK
OUT
FRAME
SERIALIZED
LVDS
OUTPUTS
217212 TA01
LTC2172-12, 65Msps,
2-Tone FFT, f_IN = 70MHz and 75MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10
20
FREQUENCY (MHz)
30
217212 TA01b
21721012fb
1