LTC4000_15 Datasheet, PDF (16/40 Pages) Linear Technology – High Voltage High Current Controller for Battery Charging and Power Management

LTC4000
Applications Information
Input Ideal Diode PMOS Selection
The input external PMOS is selected based on the expected
maximum current, power dissipation and reverse volt-
age drop. The PMOS must be able to withstand a gate to
source voltage greater than V_IGATE(ON) (15V maximum) or
the maximum regulated voltage at the IID pin, whichever
is less. A few appropriate external PMOS for a number of
different requirements are shown at Table 1.
Table 1. PMOS
PART NUMBER
R_DS(ON) AT
V_GS = 10V
(Ω)
SiA923EDJ
0.054
Si9407BDY
0.120
Si4401BDY
0.014
Si4435DDY
0.024
SUD19P06-60
0.060
Si7135DP
0.004
MAX ID
(A)
4.5
4.7
10.5
11.4
18.3
60
MAX VDS
(V) MANUFACTURER
–20
Vishay
–60
Vishay
–40
Vishay
–30
Vishay
–60
Vishay
–30
Vishay
Note that in general the larger the capacitance seen on
the IGATE pin, the slower the response of the ideal diode
driver. The fast turn off and turn on current is limited to
–0.5mA and 0.7mA typical respectively (I_{IGATE(FASTOFF)} and
I_{IGATE(FASTON)}). If the driver can not react fast enough to a
sudden increase in load current, most of the extra current
is delivered through the body diode of the external PMOS.
This increases the power dissipation momentarily. It is
important to ensure that the PMOS is able to withstand
this momentary increase in power dissipation.
The operation section also mentioned that an external 10M
pull-up resistor is recommended between the IGATE pin
and the CSP pin when the IN pin voltage is expected to
be out of its operating range, at the same time that the
external input ideal diode PMOS is expected to be com-
pletely turned off. Note that this additional pull-up resistor
increases the forward voltage regulation of the ideal diode
function (V_IID,CSP) from the typical value of 8mV.
The increase in this forward voltage is calculated according
to the following formula:
∆V_{IID,CSP REG} = V_GSON • 20k/R_IGATE
where V_GSON is the source to gate voltage required to
achieve the desired ON resistance of the external PMOS
and R_IGATE is the external pull-up resistor from the IGATE
pin to the CSP pin. Therefore, for a 10M R_IGATE resistor
and assuming a 10V V_GSON, the additional forward voltage
regulation is ∆V_{IID,CSP REG} = 20mV, and the total forward
voltage regulation is 28mV (typ). It is recommended to
set the R_IGATE such that this additional forward voltage
regulation value does not exceed 40mV.
Input Current Limit Setting and Monitoring
The regulated input current limit is set using a resistor at
the IL pin according to the following formula:
R_IS
=
V_IL
20 • I_ILIM
where V_IL is the voltage on the IL pin. The IL pin is internally
pulled up with an accurate current source of 50µA. Therefore
an equivalent formula to obtain the input current limit is:
R_IL
= ^{ILIM • RIS}
2.5µA
⇒ I_ILIM
=
R_IL
R_IS
• 2.5µA
The input current through the sense resistor is available
for monitoring through the IIMON pin. The voltage on
the IIMON pin varies with the current through the sense
resistor as follows:
V_IIMON = 20 • I_RIS • R_IS = 20 • ₍V_IN – V_{CLN )}
The regulation voltage level at the IIMON pin is clamped
at 1V with an accurate internal reference. At 1V on the
IIMON pin, the input current limit is regulated at the fol-
lowing value:
I_{ILIM(MAX )}( A)
=
0.050V
R_IS(Ω)
When this maximum current limit is desired, leave the IL
pin open or set it to a voltage >1.05V such that amplifier
A4 can regulate the IIMON voltage accurately to the internal
reference of 1V.
If the input current is noisy, add a filter capacitor to the CLN
pin to reduce the AC content. For example, when using a
buck DC/DC converter, the use of a C_CLN capacitor is strongly
recommended. Where the highest accuracy is important, pick
the value of C_CLN such that the AC content is less than or
equal to 50% of the average voltage across the sense resistor.
4000fb
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