LTC3872-1_15 Datasheet, PDF (15/20 Pages) Linear Technology – No RSENSE Current Mode Boost DC/DC Controller

LTC3872-1
Applications Information
3. Assuming a MOSFET junction temperature of 125°C,
the room temperature MOSFET R_DS(ON) should be less
than:
R_DS(ON)
≤
V_SENSE(MAX)
•
₁₊

1– D_MAX
χ
2
•I_O(MAX)
•
ρ_T
=
0.175V
•
₁₊
1– 0.39
0.4_{ • 2A}
• 1.5
≈
30mΩ
 2
The MOSFET used was the Si3460 DDV, which has a maxi-
mum R_DS(ON) of 27mW at 4.5V V_GS, a BV_DSS of greater
than 30V, and a gate charge of 13.5nC at 4.5V V_GS.
4. The diode for this design must handle a maximum DC
output current of 2A and be rated for a minimum reverse
voltage of V_OUT, or 5V. A 25A, 15V diode from On Semi-
conductor (MBRB2515L) was chosen for its high power
dissipation capability.
5. The output capacitor usually consists of a lower valued,
low ESR ceramic.
6. The choice of an input capacitor for a boost converter
depends on the impedance of the source supply and the
amount of input ripple the converter will safely tolerate.
For this particular design two 22µF Taiyo Yuden ceramic
capacitors (JMK325BJ226MM) are required (the input
and return lead lengths are kept to a few inches). As
with the output node, check the input ripple with a single
oscilloscope probe connected across the input capacitor
terminals.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3872-1. These items are illustrated graphically
in the layout diagram in Figure 8. Check the following in
your layout:
1. The Schottky diode should be closely connected between
the output capacitor and the drain of the external MOSFET.
2. The input decoupling capacitor (0.1µF) should be con-
nected closely between V_IN and GND.
3. The trace from SW to the switch point should be kept
short.
4. Keep the switching node NGATE away from sensitive
small signal nodes.
5. The V_FB pin should connect directly to the feedback
resistors. The resistive divider R1 and R2 must be con-
nected between the (+) plate of C_OUT and signal ground.
R_ITH
C_ITH
R1
IPRG
SW
I_TH
RUN/SS
LTC3872-1
V_FB
V_IN
GND
NGATE
R2
BOLD LINES INDICATE HIGH CURRENT PATHS
+ ^CIN
L1
+ ^COUT
D1
V_OUT
M1
V_IN
38721 F08
Figure 8. LTC3872-1 Layout Diagram (See PC Board Layout Checklist)
For more information www.linear.com/LTC3872-1
38721f
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