LTC3633 Datasheet, PDF (15/28 Pages) Linear Technology – Dual Channel 3A, 15V Monolithic Synchronous Step-Down Regulator

LTC3633
APPLICATIONS INFORMATION
Output Voltage Programming
Each regulator’s output voltage is set by an external resis-
tive divider according to the following equation:
V_OUT
=


0.6V _1+

R2 ^
R1_
The desired output voltage is set by appropriate selection
of resistors R1 and R2 as shown in Figure 2. Choosing
large values for R1 and R2 will result in improved zero-
load efficiency but may lead to undesirable noise coupling
or phase margin reduction due to stray capacitances
at the V_FB node. Care should be taken to route the V_FB
trace away from any noise source, such as the SW trace.
To improve the frequency response of the main control
loop, a feedforward capacitor, C_F, may be used as shown
in Figure 2.
FB
LTC3633
SGND
V_OUT
R2
C_F
R1
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Figure 2. Setting the Output Voltage
Minimum Off-Time/On-Time Considerations
The minimum off-time is the smallest amount of time that
the LTC3633 can turn on the bottom power MOSFET, trip
the current comparator and turn the power MOSFET back
off. This time is typically 40ns. For the controlled on-time
control architecture, the minimum off-time limit imposes
a maximum duty cycle of:
( ) ^DC_(MAX) ^{= 1 – f • t}_OFF(MIN)
where f is the switching frequency and t_OFF(MIN) is the
minimum off-time. If the maximum duty cycle is surpassed,
due to a dropping input voltage for example, the output
will drop out of regulation. The minimum input voltage to
avoid this dropout condition is:
( ) ^{VIN(MIN) = 1−}
V_OUT
f • t_OFF(MIN)
Conversely, the minimum on-time is the smallest dura-
tion of time in which the top power MOSFET can be in
its “on” state. This time is typically 20ns. In continuous
mode operation, the minimum on-time limit imposes a
minimum duty cycle of:
( ) ^DC_(MIN) ^{= f • t}_ON(MIN)
where t_ON(MIN) is the minimum on-time. As the equation
shows, reducing the operating frequency will alleviate the
minimum duty cycle constraint.
In the rare cases where the minimum duty cycle is
surpassed, the output voltage will still remain in regula-
tion, but the switching frequency will decrease from its
programmed value. This constraint may not be of critical
importance in most cases, so high switching frequencies
may be used in the design without any fear of severe
consequences. As the sections on Inductor and Capacitor
selection show, high switching frequencies allow the use
of smaller board components, thus reducing the footprint
of the application circuit.
Internal/External Loop Compensation
The LTC3633 provides the option to use a fixed internal
loop compensation network to reduce both the required
external component count and design time. The internal
loop compensation network can be selected by connec-
tion the ITH pin to the INTV_CC pin. To ensure stability it is
recommended that internal compensation only be used with
applications with f_SW > 1MHz. Alternatively, the user may
choose specific external loop compensation components
to optimize the main control loop transient response as
desired. External loop compensation is chosen by simply
connecting the desired network to the ITH pin.
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