LTC3622-2_15 Datasheet, PDF (15/24 Pages) Linear Technology – 17V, Dual 1A Synchronous Step-Down Regulator with Ultralow Quiescent Current

LTC3622/
LTC3622-2/LTC3622-23/5
Applications Information
resistance of C_OUT. ΔI_LOAD also begins to charge or dis-
charge C_OUT generating a feedback error signal used by the
regulator to return V_OUT to its steady state value. During
this recovery time, V_OUT can be monitored for overshoot
or ringing that indicates a stability problem.
The initial output voltage step may not be within the band-
width of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. In addition, a feedforward capacitor can be added
to improve the high frequency response, shown in Figure 2.
Capacitor C_FF provides phase lead by creating a high fre-
quency zero with R2, which improves the phase margin.
The output voltage settling behavior is related to the stabil-
ity of the closed-loop system and demonstrates the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>1µF) input capacitors.
The discharge input capacitors are effectively put in paral-
lel with C_OUT, causing a rapid drop in V_OUT. No regulator
can deliver enough current to prevent this problem if the
switch connecting to load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates
current limiting, short-circuit protection and soft-starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2 etc. are the individual losses as a percentage
of input power. Although all dissipative elements in the
circuit produce losses, three main sources usually account
for most of the losses in LTC3622 circuit: 1) I²R losses,
2) switching and biasing losses, 3) other losses.
1. I²R losses are calculated from the DC resistances of
the internal switches, R_SW, and external inductor, R_L.
In continuous mode, the average output current flows
through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both top and bottom MOSFET R_DS(ON) and the duty
cycle (DC) as follows:
R_SW =(R_DS(ON)TOP)(DC)+(R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus to obtain I²R losses:
I²R Losses = I_OUT2(R_SW + R_L)
2. The switching current is the sum of the MOSFET driver
and control currents. The power MOSFET driver current
results from switching the gate capacitance of the power
MOSFETs. Each time a power MOSFET gate is switched
from low to high to low again, a packet of charge dQ
moves from V_IN to ground. The resulting dQ/dt is a
current out of V_IN that is typically much larger than the
DC control bias current. In continuous mode, I_GATECHG
= f_OSC(Q_T + Q_B), where Q_T and Q_B are the gate charges
of the internal top and bottom power MOSFETs and
f_OSC is the switching frequency. The power loss is thus:
Switching Loss = I_GATECHG • V_IN
The gate charge loss is proportional to V_IN and f_OSC and
thus their effects will be more pronounced at higher
supply voltages and higher frequencies.
3. Other “hidden” losses such as transition loss and cop-
per trace and internal load resistances can account for
additional efficiency degradations in the overall power
system. It is very important to include these “system”
level losses in the design of a system. Transition loss
arises from the brief amount of time the top power
MOSFET spends in the saturated region during switch
node transitions. The LTC3622 internal power devices
switch quickly enough that these loses are not significant
compared to other sources. These losses plus other
losses, including diode conduction losses during dead
time and inductor core losses, generally account for
less than 2% total additional loss.
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