LTC3330 Datasheet, PDF (15/20 Pages) Linear Technology – Energy Harvesting DC/DC with Battery Backup Low Noise LDO Post Regulator

LTC3330
Operation
this point the current in the inductor is equal to IPEAK and
the IPEAK comparator will trip turning off M1 and turn-
ing on M2 causing the inductor current to ramp down to
IZERO, completing the transition from buck-boost mode
to buck mode.
V_OUT Power Good
A power good comparator is provided for the V_OUT out-
put. It transitions high the first time the LTC3330 goes
to sleep, indicating that V_OUT has reached regulation. It
transitions low when V_OUT falls to 92.5% (typical) of its
value at regulation. The PGVOUT output is referenced to
an internal rail that is generated to be the highest of V_IN2,
BAT, and V_OUT less a Schottky diode drop.
Prioritizer
The input prioritizer on the LTC3330 decides whether to use
the energy harvesting input or the battery input to power
V_OUT. If a battery is powering the buck-boost converter
and harvested energy causes a UVLO rising transition on
V_IN, the prioritizer will shut off the buck-boost and turn on
the buck, orchestrating a smooth transition that maintains
regulation of V_OUT. When harvestable energy disappears,
the prioritizer will first poll the battery voltage. If the battery
voltage is above 1.8V the prioritizer will switch back to
the buck-boost while maintaining regulation. If the bat-
tery voltage is below 1.8V the buck-boost is not enabled
and V_OUT cannot be supported until harvestable energy
is again available. If either BAT or V_IN is grounded, the
prioritizer allows the other input to run if its input is high
enough for operation.
When the prioritizer selects the V_IN input the current on
the BAT input drops to zero. However, if the voltage on
BAT is higher than V_IN2, 150nA (typical) will appear as
quiescent current on BAT due to internal level shifting.
This only affects a small range of battery voltages and
UVLO settings.
A digital output, EH_ON, is low when the prioritizer has
selected the BAT input and is high when the prioritizer has
selected the V_IN input. The EH_ON output is referenced
to V_IN3.
Low Drop Out Regulator
An integrated low drop out regulator (LDO) is available with
its own input, LDO_IN. It will regulate LDO_OUT to seven
different output voltages based on the LDO[2:0] pins. An
eighth mode is provided to turn the LDO into a current-
limited switch in which the PMOS is always on. LDO_EN
enables the LDO when high and when low eliminates all
quiescent current on LDO_IN. The LDO is designed to
provide 50mA over a range of LDO_IN and LDO_OUT
combinations. A current limit set above 50mA is available
to dial back the current if the output is grounded or the
load demands more than 50mA. The LDO also features a
1ms soft-start for smooth output start-up.
A power good signal on the PGLDO pin indicates when
the voltage at LDO_OUT rises above 92.5% (typical) of its
final value, or after tripped, when the LDO_OUT falls below
90.0% of that value. The PGLDO output is referenced to
an internal rail that is generated to be the highest of V_IN2,
BAT, and V_OUT less a Schottky diode drop.
Supercapacitor
An integrated supercapacitor balancer with 165nA of
quiescent current is available to balance a stack of two
supercapacitors. Typically the input, SCAP, will tie to
V_OUT to allow for increased energy storage at V_OUT with
supercapacitors. The BAL pin is tied to the middle of the
stack and can source and sink 10mA to regulate the BAL
pin’s voltage to half that of the SCAP pin’s voltage. To
disable the balancer and its associated quiescent current
the SCAP and BAL pins can be tied to ground.
For more information www.linear.com/LTC3330
3330p
15