LTC3330 Datasheet, PDF (11/20 Pages) Linear Technology – Energy Harvesting DC/DC with Battery Backup Low Noise LDO Post Regulator

LTC3330
Pin Functions
OUT0, OUT1, OUT2 (Pins 30, 31, 32): V_OUT Voltage Select
Bits. Tie high to V_IN3 or low to GND to select the desired
V_OUT (see Table 1). Do not float.
GND (Exposed Pad Pin 11): Ground. The exposed pad
must be connected to a continuous ground plane on the
second layer of the printed circuit board by several vias
directly under the LTC3330.
Block Diagram
10 ^VIN
20V
AC1
8
AC2
9
26 ^VIN3
V_REF
BANDGAP
REFERENCE
BAT
16
EH_ON
29
UVLO
UVLO_SET
INTERNAL
RAIL
GENERATION
SLEEP
PRIORITZER
BUCK
CONTROL
ILIM_SET
BUCK-BOOST
CONTROL
V_REF –
SLEEP
+
CAP
11
SW
12
V_IN2
3
GND
33
SWA
15
SWB
14
V_OUT
13
PGVOUT
28
PGLDO
27
+
SLEEP
–
0.925*V_REF
–
0.9*V_REF
+
V_REF –
+
UVLO_SET
ILIM_SET
4
3
3
3
UV[3:0]
IPK[2:0]
OUT[2:0]
LDO[2:0]
4, 5, 6, 7
19, 18, 17
32, 31, 30
22, 23, 24
LDO_EN ₂₅
LDO_IN ₂₁
LDO_OUT ₂₀
SCAP
1
+
BAL
2
–
3330 BD
For more information www.linear.com/LTC3330
3330p
11