LTC1750_15 Datasheet, PDF (15/20 Pages) Linear Technology – 14-Bit, 80Msps Wide Bandwidth ADC

LTC1750
APPLICATIO S I FOR ATIO
2V
V_CM
4.7µF
10k
1V
SENSE ^LTC1750
10k
1µF
1750 F06a
Figure 6a. 2V Range ADC
5V
0.1µF
4
6
LT1790-1.25
1, 2
2V
2.5k
1µF 10k
V_CM
4.7µF
SENSE ^LTC1750
1µF
1750 F06b
Figure 6b. 2V Range ADC with External Reference
Input Range
The LTC1750 performance may be optimized by adjusting
the ADC’s input range to meet the requirements of the
application. For lower input frequency applications
(<80MHz), the highest input range of ±1.125V (2.25V) will
provide the best SNR while maintaining excellent SFDR.
For higher input frequencies (>80MHz), a lower input
range will provide better SFDR performance with a reduc-
tion in SNR.
The input range of the ADC is determined as ±V_REF/A_PGA,
where V_REF is the reference voltage (described in the
Reference Operation section) and A_PGA is the effective
PGA gain. Table 1 shows the input range of the ADC versus
the state of the two pins, PGA and SENSE.
Driving the Encode Inputs
The noise performance of the LTC1750 can depend on the
encode signal quality as much as on the analog input. The
ENC/ENC inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a 2V
bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
The encode inputs have a common mode range of 1.8V to
V_DD. Each input may be driven from ground to V_DD for
single-ended drive.
Table 1
PGA
0
1
0
1
0
1
V_SENSE
= V_DD
= V_DD
= GND
= GND
0.7V < V_SENSE < 1.125V
0.7V < V_SENSE < 1.125V
INPUT RANGE
2.25V_P-P Differential
1.35V_P-P Differential
1.4V_P-P Differential
0.84V_P-P Differential
2 × V_SENSE
Peak-to-Peak Differential
1.2 × V_SENSE
Peak-to-Peak Differential
COMMENTS
Best Noise, SNR = 75.5dB. Good SFDR, >82dB Up to 100MHz
Improved High Frequency Distortion. SNR = 73dB. SFDR > 80dB Up to 250MHz
Reduced Internal Reference Mode with PGA = 0. Provides Similar Input Range as
V_SENSE = V_DD and PGA = 0 But with Worse Noise. SNR = 71.4dB
Smallest Possible Input Span. Useful for Improved Distortion at Very High
Frequencies, But with Reduced Noise Performance. SNR = 69dB
Adjustable Input Range with Better Noise Performance. SNR = 75.5dB with
V_SENSE = 1.125V, SNR = 71.4dB with V_SENSE = 0.7V
Adjustable Input Range with Better High Frequency Distortion. SNR = 73dB with
V_SENSE = 1.125V, SNR = 69dB with V_SENSE = 0.7V
1750f
15