LT1002 Datasheet, PDF (15/16 Pages) Linear Technology – Dual, Matched Precision Operational Amplifier

LT1002
SCHE ATIC DIAGRA
V+
6k
6k
Q27
NULL
40k ^NULL 40k
Q28
Q5
Q6
Q7
Q3
Q8
Q4
Q29
Q11 Q13 Q14 Q12
Q24
Q25
1.5k
25k
3k
55pF
20pF
Q33
+ ₅₀₀
IN
– ₅₀₀
IN
Q1A Q1B
Q2B Q2A
Q10
1_{/2 LT1002}
Q9
V–
30pF
3k
T1
180 Ω Q20
Q15
2k
Q17
Q19
Q16
2k
Q18
Q26
Q21
Q34
Q22
Q30
8k 120
Q23
240
Q31
20
OUT
20
Q32
1002 SS
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
N Package
14-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
J Package
14-Lead CERDIP (Narrow 0.300, Hermetic)
(LTC DWG # 05-08-1110)
0.770*
(19.558)
MAX
14 13 12 11 10 9
8
0.255 ± 0.015*
(6.477 ± 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.130 ± 0.005
(3.302 ± 0.127)
1
2
3
4
5
6
7
0.045 – 0.065
(1.143 – 1.651)
0.009 – 0.015
(0.229 – 0.381)
0.015
(0.380)
MIN
+0.025
0.325 _–0.015
( ) ^8.255
+0.635
–0.381
0.125
(3.175)
MIN
0.005
(0.125)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
0.065
(1.651)
TYP
0.018 ± 0.003
(0.457 ± 0.076)
N14 0695
LT1002ACN
LT1002CN
T_JMAX
125°C
θ_JA
100°C/W
CORNER LEADS OPTION
(4 PLCS)
0.005
(0.127)
MIN
0.045 – 0.068
(1.143 – 1.727)
FULL LEAD
OPTION
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION
0.025
(0.635)
RAD TYP
0.300 BSC
(0.762 BSC)
0.785
(19.939)
MAX
14 13 12 11 10 9
8
0.220 – 0.310
(5.588 – 7.874)
1
2
3
4
5
6
7
0.200
(5.080)
MAX
0.015 – 0.060
(0.381 – 1.524)
0.008 – 0.018
(0.203 – 0.457)
0° – 15°
0.385 ± 0.025
(9.779 ± 0.635)
0.045 – 0.068
(1.143 – 1.727)
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP OR TIN PLATE LEADS.
0.014 – 0.026
(0.360 – 0.660)
LT1002ACJ
LT1002CJ
LT1002AMJ
LT1002MJ
T_JMAX
125°C
125°C
θ_JA
100°C/W
100°C/W
0.100 ± 0.010
(2.540 ± 0.254)
0.125
(3.175)
MIN
J14 0694
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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