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LTC4000-1 Datasheet, PDF (14/40 Pages) Linear Technology – High Voltage High Current Controller for Battery Charging with Maximum Power Point Control
LTC4000-1
Operation
CSP pin (source). The controller (A1) regulates the external
PMOS by driving the gate of the PMOS device such that the
voltage drop across IID and CSP is 8mV (typical). When
the external PMOS ability to deliver a particular current
with an 8mV drop across its source and drain is exceeded,
the voltage at the gate clamps at VIGATE(ON) and the PMOS
behaves like a fixed value resistor (RDS(ON)).
Input Voltage Regulation
One of the loops driving the ITH and CC pins is the input
voltage regulation loop (Figure 2). This loop prevents the
input voltage from dropping below the programmed level.
RIS
IN
DC/DC INPUT
CIN
CCLN
(OPTIONAL)
IN
CLN
RIFB1
IFB
RIFB2
–
1V +
A4
LTC4000-1
CC
–
ITH
+
CC
RC
TO DC/DC
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Figure 2. Input Voltage Regulation Loop
When the input source is high impedance, the input volt-
age drops as the load current increases. In that case there
exists a voltage level at which the available power from
the input is maximum. For example, solar panels often
specify VMP, corresponding to the panel voltage at which
maximum power is achieved. With the LTC4000-1 input
voltage regulation, this maximum power voltage level can
be programmed at the IFB pin. The input voltage regulation
loop regulates ITH to ensure that the input voltage level
does not drop below this programmed level.
Battery Charger Overview
In addition to the input voltage regulation loop, the
LTC4000-1 regulates charge current, battery voltage and
output voltage.
When a battery charge cycle begins, the battery charger
first determines if the battery is over-discharged. If the
battery feedback voltage is below VLOBAT, an automatic
trickle charge feature uses the charge current regulation
14
loop to set the battery charge current to 10% of the pro-
grammed full-scale value. If the TMR pin is connected
to a capacitor or open, the bad battery detection timer is
enabled. When this bad battery detection timer expires
and the battery voltage is still below VLOBAT, the battery
charger automatically terminates and indicates, via the
FLT and CHRG pins, that the battery was unresponsive
to charge current.
Once the battery voltage is above VLOBAT, the charge current
regulation loop begins charging in full power constant-
current mode. In this case, the programmed full charge
current is set with a resistor on the CL pin.
Depending on available input power and external load
conditions, the battery charger may not be able to charge
at the full programmed rate. The external load is always
prioritized over the battery charge current. The input volt-
age programming is always observed, and only additional
power is available to charge the battery. When system
loads are light, battery charge current is maximized.
Once the float voltage is achieved, the battery float volt-
age regulation loop takes over from the charge current
regulation loop and initiates constant voltage charging. In
constant voltage charging, charge current slowly declines.
Charge termination can be configured with the TMR pin
in several ways. If the TMR pin is tied to the BIAS pin,
C/X termination is selected. In this case, charging is
terminated when constant voltage charging reduces the
charge current to the C/X level programmed at the CX
pin. Connecting a capacitor to the TMR pin selects the
charge timer termination and a charge termination timer
is started at the beginning of constant voltage charging.
Charging terminates when the termination timer expires.
When continuous charging at the float voltage is desired,
tie the TMR pin to GND to disable termination.
Upon charge termination, the PMOS connected to BGATE
behaves as an ideal diode from BAT to CSN. The diode
function prevents charge current but provides current
to the system load as needed. If the system load can be
completely supplied from the input, the battery PMOS turns
off. While terminated, if the input voltage loop is not in
regulation, the output voltage regulation loop takes over to
ensure that the output voltage at CSP remains in control.
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