LTC3642 Datasheet, PDF (14/20 Pages) Linear Technology – High Effi ciency, High Voltage 50mA Synchronous Step-Down Converter

LTC3642
APPLICATIONS INFORMATION
To increase the duration of the reference voltage soft-start,
place a capacitor from the SS pin to ground. An internal
5μA pull-up current will charge this capacitor, resulting in
a soft-start ramp time given by:
t_SS
=
C_SS
•
0.8V
5μA
When the LTC3642 detects a fault condition (input supply
undervoltage or overvoltage) or when the RUN pin falls
below 1.1V, the SS pin is quickly pulled to ground and the
internal soft-start timer is reset. This ensures an orderly
restart when using an external soft-start capacitor.
The duration of the 1ms internal peak current soft-start
may be increased by placing a capacitor from the I_SET pin
to ground. The peak current soft-start will ramp from 25mA
to the final peak current value determined by a resistor
from I_SET to ground. A 1μA current is sourced out of the
I_SET pin. With only a capacitor connected between I_SET
and ground, the peak current ramps linearly from 25mA
to 115mA, and the peak current soft-start time can be
expressed as:
t_SS(ISET)
=
C_ISET
•
0.8V
1μA
A linear ramp of peak current appears as a quadratic
waveform on the output voltage. For the case where the
peak current is reduced by placing a resistor from I_SET
to ground, the peak current offset ramps as a decaying
exponential with a time constant of R_ISET • C_ISET. For this
case, the peak current soft-start time is approximately
3 • R_ISET • C_ISET.
Unlike the SS pin, the I_SET pin does not get pulled to
ground during an abnormal event; however, if the I_SET
pin is floating (programmed to 115mA peak current),
the SS and I_SET pins may be tied together and connected
to a capacitor to ground. For this special case, both the
peak current and the reference voltage will soft-start on
power-up and after fault conditions. The ramp time for
this combination is C_SS(ISET) • (0.8V/6μA).
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V_IN operating current and I²R losses. The V_IN
operating current dominates the efficiency loss at very
low load currents whereas the I²R loss dominates the
efficiency loss at medium to high load currents.
1. The V_IN operating current comprises two components:
The DC supply current as given in the electrical charac-
teristics and the internal MOSFET gate charge currents.
The gate charge current results from switching the gate
capacitance of the internal power MOSFET switches.
Each time the gate is switched from high to low to
high again, a packet of charge, dQ, moves from V_IN to
ground. The resulting dQ/dt is the current out of V_IN
that is typically larger than the DC bias current.
2. I²R losses are calculated from the resistances of the
internal switches, R_SW, and external inductor R_L. When
switching, the average output current flowing through
the inductor is “chopped” between the high side PMOS
switch and the low side NMOS switch. Thus, the series
resistance looking back into the switch pin is a function
of the top and bottom switch R_DS(ON) values and the
duty cycle (DC = V_OUT/V_IN) as follows:
R_SW = (R_DS(ON)TOP)DC + (R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain the I²R losses, simply add
R_SW to R_L and multiply the result by the square of the
average output current:
I²R Loss = I_O2(R_SW + R_L)
3642f
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