LTC3621-2_15 Datasheet, PDF (14/18 Pages) Linear Technology – 17V, 1A Synchronous Step-Down Regulator with 3.5A Quiescent Current

LTC3621/LTC3621-2
Applications Information
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3621 (refer to Figure 3). Check the following in
your layout:
5. Keep sensitive components away from the SW pin. The
feedback resistors and INTV_CC bypass capacitors should
be routed away from the SW trace and the inductor.
6. A ground plane is preferred.
7. Flood all unused areas on all layers with copper, which
reduces the temperature rise of power components.
These copper areas should be connected to GND.
L1
C_IN
V_IN
V_OUT
GND
C_OUT
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Figure 3. Sample PCB Layout
1. Do the capacitors C_IN connect to the V_IN pin and GND
pin as close as possible? These capacitors provide the
AC current to the internal power MOSFETs and their
drivers.
2. Are C_OUT and L closely connected? The (–) plate of
C_OUT returns current to GND.
3. The resistive divider, R1 and R2, must be connected
between the (+) plate of C_OUT and a ground line ter-
minated near GND. The feedback signal V_FB should be
routed away from noisy components and traces, such
as the SW line, and its trace should be minimized. Keep
R1 and R2 close to the IC.
4. Solder the exposed pad (Pin 7 for DFN, Pin 9 for MSOP)
on the bottom of the package to the GND plane. Connect
this GND plane to other layers with thermal vias to help
dissipate heat from the LTC3621.
Design Example
As a design example, consider using the LTC3621 in an
application with the following specifications:
V_IN = 10.8V to 13.2V
V_OUT = 3.3V
I_OUT(MAX) = 1A
I_OUT(MIN) = 0A
f_SW = 2.25MHz
Because efficiency and quiescent current is important at
both 500mA and 0A current states, Burst Mode operation
will be utilized.
Given the internal oscillator of 2.25MHz, we can calcu-
late the inductor value for about 40% ripple current at
maximum V_IN:
L
=
 3.3V 
_{2.25MHz • 0.4A}
_1–
3.3V 
13.2V^
= 2.75µH
Given this, a 2.7µH or 3.3µH, >1.2A inductor would suffice.
C_OUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, a
22µF ceramic capacitor will be used.
C_IN should be sized for a maximum current rating of:
I_RMS
=
1A
 3.3V 
_13.2V
13.2V
 _3.3V
–
1^
1/2
=
0.43A
Decoupling the V_IN pin with 10µF ceramic capacitors is
adequate for most applications.
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