LTC3388-1_15 Datasheet, PDF (14/20 Pages) Linear Technology – 20V High Efficiency Nanopower Step-Down Regulator

LTC3388-1/LTC3388-3
APPLICATIONS INFORMATION
Introduction
The basic LTC3388-1/LTC3388-3 application circuit is
shown on the front page. External components are se-
lected based on the performance requirements of the
application.
Input Capacitor Selection
The input capacitor at V_IN should be selected to adequately
bypass the LTC3388-1/LTC3388-3 and filter the switching
current presented by the buck regulator. The V_IN capaci-
tor should be rated to withstand the highest voltage ever
present at V_IN. It should be placed as close as possible
to the LTC3388-1/LTC3388-3 to force the high frequency
switching current into a tight local loop to minimize EMI.
A 2.2μF ceramic X7R or X5R capacitor should be adequate
for bypassing.
High ripple current, high voltage rating, and low ESR make
ceramic capacitors ideal for switching regulator applica-
tions. However, care must be taken when these capacitors
are used at the input and output. When a ceramic capacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, V_IN. A sudden inrush of cur-
rent through the long wires can potentially cause a voltage
spike at V_IN large enough to damage the part.
For such applications with inductive source impedance,
such as a long wire, a series RC network may be required
in parallel with C_IN to dampen the ringing of the input
supply. Figure 5 shows this circuit and the typical values
required to dampen the ringing. The RC resistor may be
replaced by a single electrolytic capacitor that has an ESR
equivalent to the needed series resistance of the network.
See Application Note 88 for a complete discussion of this
phenomenon.
Output Capacitor Selection
The duration for which the regulator sleeps depends
on the load current and the size of the output capacitor.
The sleep time decreases as the load current increases
and/or as the output capacitor decreases. The DC sleep
hysteresis window, V_HYST, is ±8mV and ±16mV around
the programmed output voltage on the LTC3388-1 and
LTC3388-3 respectively. Ideally this means that the sleep
time is determined by the following equation:
t_SLEEP
= C_OUT
V_HYST
I_LOAD
This is true for output capacitors on the order of 100μF
or larger, but as the output capacitor decreases towards
10μF delays in the internal sleep comparator along with
the load current may result in the V_OUT voltage slewing
past the ±8mV/±16mV thresholds. This will lengthen the
sleep time and increase V_OUT ripple. A capacitor less than
10μF is not recommended as V_OUT ripple could increase
to an undesirable level.
L_IN
R  ^LIN
C_IN
4 • C_IN
LTC3388-1/
LTC3388-3
V_IN
338813 F05
C_IN
Figure 5. Series RC to Reduce V_IN Ringing
338813f
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