LTC3388-1_15 Datasheet, PDF (11/20 Pages) Linear Technology – 20V High Efficiency Nanopower Step-Down Regulator

LTC3388-1/LTC3388-3
OPERATION
The LTC3388-1/LTC3388-3 is an ultralow quiescent
current power supply designed to maintain a regulated
output voltage by means of a nanopower high efficiency
synchronous buck regulator.
Undervoltage Lockout (UVLO)
When the voltage on V_IN rises above the UVLO rising
threshold the buck converter is enabled and charge is
transferred from the input capacitor to the output capacitor.
If V_IN falls below the UVLO falling threshold the part will
re-enter UVLO. In UVLO the quiescent current is approxi-
mately 400nA and the buck converter is disabled.
Internal Rail Generation
Two internal rails, CAP and V_IN2, are generated from V_IN and
are used to drive the high side PMOS and low side NMOS
of the buck converter, respectively. Additionally the V_IN2
rail serves as logic high for EN, STBY, and output voltage
select bits D0 and D1. The V_IN2 rail is regulated at 4.6V
above GND while the CAP rail is regulated at 4.8V below
V_IN. The V_IN2 and CAP rails are not intended to be used
as external rails. Bypass capacitors are connected to the
CAP and V_IN2 pins to serve as energy reservoirs for driving
the buck switches. When V_IN is below 4.6V, V_IN2 is equal
to V_IN. CAP is at GND until V_IN rises above 4.8V. Figure 1
shows the ideal V_IN, V_IN2 and CAP relationship.
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16
14
12
10
8
6
4
2
0
0
V_IN
CAP
5
10
V_IN (V)
V_IN2
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Figure 1. Ideal V_IN, V_IN2 and CAP Relationship
Buck Operation
The buck regulator uses a hysteretic voltage algorithm
to control the output through internal feedback from the
V_OUT sense pin. The buck converter charges an output
capacitor through an inductor to a value slightly higher than
the regulation point. It does this by ramping the inductor
current up to 150mA through an internal PMOS switch
and then ramping it down to 0mA through an internal
NMOS switch. This efficiently delivers energy to the output
capacitor. The ramp rate is determined by V_IN, V_OUT, and
the inductor value. When the buck brings the output volt-
age into regulation the converter enters a low quiescent
current sleep state that monitors the output voltage with
a sleep comparator. During this operating mode load cur-
rent is provided by the buck output capacitor. When the
output voltage falls below the regulation point the buck
regulator wakes up and the cycle repeats. This hysteretic
method of providing a regulated output reduces losses
associated with FET switching and maintains an output
at light loads. The buck delivers a minimum of 50mA of
average load current when it is switching.
When the sleep comparator signals that the output has
reached the sleep threshold the buck converter may be
in the middle of a cycle with current still flowing through
the inductor. Normally both synchronous switches would
turn off and the current in the inductor would freewheel
to zero through the NMOS body diode. The LTC3388-1/
LTC3388-3 keeps the NMOS switch on during this time to
prevent the conduction loss that would occur in the diode
if the NMOS were off. If the PMOS is on when the sleep
comparator trips, the NMOS will turn on immediately in
order to ramp down the current. If the NMOS is on it will
be kept on until the current reaches zero.
Though the quiescent current when the buck is switching
is much greater than the sleep quiescent current, it is still
a small percentage of the average inductor current which
results in high efficiency over most load conditions. The
buck operates only when the output voltage discharges
to the sleep falling threshold. Thus, the buck operating
quiescent current is averaged with the low sleep quiescent
current. This allows the converter to remain very efficient
at loads as low as 10μA.
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