LTC3588-1 Datasheet, PDF (13/20 Pages) Linear Technology – Piezoelectric Energy Harvesting Power Supply

APPLICATIONS INFORMATION
LTC3588-1
1μF
6V
10μF
25V
4.7μF
6V
PZ1
PZ2
V_IN
PGOOD
CAP ^LTC3588-1 SW
V_IN2
V_OUT
D1
D0
GND
10μH
EN
T_X
3.3V ^{MICROPROCESSOR}
CORE
GND
47μF
6V
OUTPUT
VOLTAGE
20mV/DIV
AC-COUPLED
LOAD
CURRENT
25mA/DIV
5mA
35881 F05a
V_IN = 5V
250μs/DIV
L = 10μH, C_OUT = 47μF
LOAD STEP BETWEEN 5mA and 55mA
Figure 5. 3.3V Piezoelectric Energy Harvester Powering a Microprocessor
with a Wireless Transmitter and 50mA Load Step Response
35881 F05b
PGOOD Signal
The PGOOD signal can be used to enable a sleeping
microprocessor or other circuitry when V_OUT reaches
regulation, as shown in Figure 5. Typically V_IN will be
somewhere between the UVLO thresholds at this time
and a load could only be supported by the output capaci-
tor. Alternatively, waiting a period of time after PGOOD
goes high would let the input capacitor accumulate more
energy allowing load current to be maintained longer as
the buck efficiently transfers that energy to the output.
While active, a microprocessor may draw a small load
when operating sensors, and then draw a large load to
transmit data. Figure 5 shows the LTC3588-1 responding
smoothly to such a load step.
Input and Output Capacitor Selection
The input and output capacitors should be selected based
on the energy needs and load requirements of the ap-
plication. In every case the V_IN capacitor should be rated
to withstand the highest voltage ever present at V_IN.
For 100mA or smaller loads, storing energy at the input
takes advantage of the high voltage input since the buck
can deliver 100mA average load current efficiently to the
output. The input capacitor should then be sized to store
enough energy to provide output power for the length of
time required. This may involve using a large capacitor,
letting V_IN charge to a high voltage, or both. Enough energy
should be stored on the input so that the buck does not
reach the UVLO falling threshold which would halt energy
transfer to the output. In general:
( ) ^PLOAD^tLOAD
=
1
2
ηC_IN
V_IN2 − V_UVLOFALLING2
V_UVLOFALLING ≤ V_IN ≤ V_SHUNT
The above equation can be used to size the input capaci-
tor to meet the power requirements of the output for the
desired duration. Here η is the average efficiency of the
buck converter over the input range and V_IN is the input
voltage when the buck begins to switch. This equation
may overestimate the input capacitor necessary since load
current can deplete the output capacitor all the way to the
lower PGOOD threshold. It also assumes that the input
source charging has a negligible effect during this time.
The duration for which the regulator sleeps depends on
the load current and the size of the output capacitor. The
sleep time decreases as the load current increases and/or
as the output capacitor decreases. The DC sleep hysteresis
window is ±12mV around the programmed output volt-
age. Ideally this means that the sleep time is determined
by the following equation:
t_SLEEP
= C_OUT
24mV
I_LOAD
35881f
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