LTC3588-1 Datasheet, PDF (10/20 Pages) Linear Technology – Piezoelectric Energy Harvesting Power Supply

LTC3588-1
OPERATION
UVLO falling threshold before the output voltage reaches
regulation, the buck converter will shut off and will not
be turned on until the input voltage again rises above the
UVLO rising threshold. During this time the output voltage
will be loaded by less than 100nA. When the buck brings
the output voltage into regulation the converter enters a
low quiescent current sleep state that monitors the output
voltage with a sleep comparator. During this operating mode
load current is provided by the buck output capacitor. When
the output voltage falls below the regulation point the buck
regulator wakes up and the cycle repeats. This hysteretic
method of providing a regulated output reduces losses
associated with FET switching and maintains an output
at light loads. The buck delivers a minimum of 100mA of
average load current when it is switching.
When the sleep comparator signals that the output has
reached the sleep threshold the buck converter may be
in the middle of a cycle with current still flowing through
the inductor. Normally both synchronous switches would
turn off and the current in the inductor would freewheel
to zero through the NMOS body diode. The LTC3588-1
keeps the NMOS switch on during this time to prevent the
conduction loss that would occur in the diode if the NMOS
were off. If the PMOS is on when the sleep comparator
trips the NMOS will turn on immediately in order to ramp
down the current. If the NMOS is on it will be kept on until
the current reaches zero.
Though the quiescent current when the buck is switching
is much greater than the sleep quiescent current, it is still
a small percentage of the average inductor current which
results in high efficiency over most load conditions. The
buck operates only when sufficient energy has been ac-
cumulated in the input capacitor and the length of time the
converter needs to transfer energy to the output is much
less than the time it takes to accumulate energy. Thus, the
buck operating quiescent current is averaged over a long
period of time so that the total average quiescent current
is low. This feature accommodates sources that harvest
small amounts of ambient energy.
Four selectable voltages are available by tying the output
select bits, D0 and D1, to GND or V_IN2. Table 1 shows
the four D0/D1 codes and their corresponding output
voltages.
10
Table 1. Output Voltage Selection
D1
D0
0
0
V_OUT
V_OUT QUIESCENT CURRENT (I_VOUT)
1.8V
44nA
0
1
2.5V
62nA
1
0
3.3V
81nA
1
1
3.6V
89nA
The internal feedback network draws a small amount of
current from V_OUT as listed in Table 1.
Power Good Comparator
A power good comparator produces a logic high referenced
to V_OUT on the PGOOD pin the first time the converter
reaches the sleep threshold of the programmed V_OUT,
signaling that the output is in regulation. The PGOOD pin
will remain high until V_OUT falls to 92% of the desired
regulation voltage. Several sleep cycles may occur during
this time. Additionally, if PGOOD is high and V_IN falls below
the UVLO falling threshold, PGOOD will remain high until
V_OUT falls to 92% of the desired regulation point. This
allows output energy to be used even if the input is lost.
Figure 2 shows the behavior for V_OUT = 3.6V and no load.
At t = 75s V_IN becomes high impedance and is discharged
by the quiescent current of the LTC3588-1 and through
servicing V_OUT which is discharged by its own leakage
current. V_IN crosses UVLO falling but PGOOD remains high
until V_OUT decreases to 92% of the desired regulation point.
The PGOOD pin is designed to drive a microprocessor or
other chip I/O and is not intended to drive higher current
loads such as an LED.
6
C_VIN = C_VOUT = 100μF
5
V_IN
4
V_IN = UVLO FALLING
V_OUT
3
2
PGOOD
1
0
0
100
200
300
TIME (s)
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Figure 2. PGOOD Operation During Transition to UVLO
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