LTC3562 Datasheet, PDF (13/20 Pages) Linear Technology – I2C Quad Synchronous Step-Down DC/DC Regulator 2 × 600mA, 2 × 400mA

LTC3562
OPERATION
ADDRESS
WR
11 001010
SUB-ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
DATA BYTE
B7 B6 B5 B4 B3 B2 B1 B0
START
STOP
SDA
1 1 0 0 1 0 1 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 7 6 5 4 3 2 1 0 ACK
SCL
1 2 3 4 5 6 7 89 1 2 3 4 5 6 7 89 1 2 3 4 5 6 7 8 9
3562 F03
Figure 3. Bit Assignments
SDA
t_LOW
t_{SU, DAT}
SCL
t_{HD, STA}
START
CONDITION
t_HIGH
t_r
t_f
t_{HD, DAT}
t_{SU, STA}
t_{HD, STA}
t_SP
REPEATED START
CONDITION
Figure 4. Timing Parameters
t_BUF
t_{SU, STO}
3562 F04
STOP
CONDITION
START
CONDITION
Table 1. Write Word Protocol Used by the LTC3562
1
7
1
1
8
1
8
1
1
S
Slave Address
WR
A
*Sub-Address
A
Data Byte
A
P**
S = Start Condition, WR = Write Bit = 0, A = Acknowledge, P = Stop Condition
* The sub-address uses only the first four most significant bits, A7, A6, A5, and A4, for sub-addressing. The two least significant bits, A1 and A0, are
used to program the regulator operating mode.
**Stop can be delayed until all of the data registers have been written.
Table 2. Sub-Address and Data Byte Mapping
SUB-ADDRESS BYTE
DATA BYTE
A7
A6
A5
A4
A3 A2 A1 A0
B7
B6 B5 B4 B3 B2 B1 B0
PROGRAM PROGRAM PROGRAM PROGRAM
R600A
R400A
R600B
R400B
NOT USED
REGULATOR
OPERATING
MODE
(SEE TABLE 3)
ENABLE
REGULATOR
DAC CODE
(See Tables 4, 5 and 6)
3562fa
13