LTC3562 Datasheet, PDF (12/20 Pages) Linear Technology – I2C Quad Synchronous Step-Down DC/DC Regulator 2 × 600mA, 2 × 400mA

LTC3562
OPERATION
I²C Interface
The LTC3562 may communicate with a host (master) using
the standard I²C 2-wire interface. The Timing Diagram in
Figure 4 shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 SMBus Accelerator,
are required on these lines. The LTC3562 is a receive-only
(slave) device. The I²C control signals, SDA and SCL are
scaled internally to the DV_CC supply. DV_CC should be con-
nected to the same power supply as the microcontroller
generating the I²C signals.
The I²C port has an undervoltage lockout on the DV_CC
pin. When DV_CC is below approximately 1V, the I²C serial
port is cleared and the two switching Type-A regulators
are set to full scale.
Bus Speed
The I²C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I²C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
START and STOP Conditions
A bus master signals the beginning of a communication
to a slave device by transmitting a start condition. A start
condition is generated by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a stop condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for communication with another I²C
device.
Byte Format
Each byte sent to the LTC3562 must be 8 bits long fol-
lowed by an extra clock cycle for the Acknowledge bit to
be returned by the LTC3562. The data should be sent to
the LTC3562 most significant bit (MSB) first.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave (LTC3562) lets the master know
that the latest byte of information was received. The
Acknowledge-related clock pulse is generated by the
master. The master releases the SDA line (HIGH) during
the Acknowledge clock cycle. The slave-receiver must pull
down the SDA line during the Acknowledge clock pulse
so that it remains a stable low during the high period of
this clock pulse.
Slave Address Byte
The LTC3562 responds to only one 7-bit address which
has been factory programmed to 11001010. The eighth
bit of the address byte (R/W) must be 0 for the LTC3562
to recognize the address since it is a write-only device.
This effectively forces the address to be 8 bits long where
the least significant bit of the address is 0. If the correct
7-bit address is given but the R/W bit is 1, the LTC3562
will not respond.
Sub-Address Byte
The sub-address byte uses bits A7 through A4 to specify
the regulator(s) being programmed by that particular
three-byte sequence (refer to Table 2). A specific regulator
gets programmed if its corresponding sub-address bit is
high, whereas the regulator ignores the 3-byte sequence
if its sub-address bit is low. Note that multiple regulators
can be programmed by the same 3-byte sequence if more
than one of the sub-address bits are high. Bits A1 and A0
of the sub-address byte are used to program the operating
mode (Table 3). Bits A3 and A2 of the sub-address byte
are not used.
Data Byte
The data byte only affects the regulators that are specified
to be programmed by the sub-address byte. The MSB
of the data byte (B7) is used to enable or disable the
regulator(s) being programmed. A high B7 indicates an
enable command, whereas a low B7 indicates a shutdown
command.
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