LTC3549 Datasheet, PDF (13/16 Pages) Linear Technology – 250mA Low VIN Buck Regulator in 2mm × 3mm DFN

LTC3549
APPLICATIO S I FOR ATIO
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3549. These items are also illustrated graphically
in the layout diagram of Figure 3. Check the following in
your layout.
1. Does the capacitor C_IN connect to the power V_IN (Pin 1)
and GND (Pins 2, 7) as close as possible? This capacitor
provides the AC current to the internal power MOSFETs
and their drivers.
2. Are the C_OUT and L1 closely connected? The (–) plate of
C_OUT returns current to GND and the (–) plate of C_IN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C_OUT and a ground sense line
terminated near GND (Exposed Pad). The feedback
signals V_FB should be routed away from noisy compo-
nents and traces, such as the SW line (Pin 3), and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor C_IN and the resistors R1 and R2
should be routed away from the SW traces and the
inductors.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point. They should not share the high current path of
C_IN or C_OUT.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to V_IN or G_ND.
Figure 3a. Buck Regulator Top Layer
Figure 3b. Buck Regulator Bottom Layer
3549f
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