LTC3448_15 Datasheet, PDF (13/20 Pages) Linear Technology – 1.5MHz/2.25MHz, 600mA Synchronous Step-Down Regulator with LDO Mode

LTC3448
APPLICATIO S I FOR ATIO
with C_OUT, causing a rapid drop in V_OUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C_LOAD).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3448. These items are also illustrated graphically in
Figures 7 and 8. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V_IN trace should be kept short, direct and
wide.
2. Does the V_FB pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C_OUT and ground.
3. Does the (+) plate of C_IN connect to V_IN as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node, SW, away from the sensitive
V_FB node.
5. Keep the (–) plates of C_IN and C_OUT as close as possible.
Design Example
As a design example, assume the LTC3448 is used in a
single lithium-ion battery-powered cellular phone
application. The V_IN will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.6A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
L
V_IN
4
C_IN
8
V_IN
RUN
5
SW
V_OUT ²
3
MODE
R_FB2
V_OUT
C_OUT
C_FF
LTC3448
6
1
FREQ
7 _SYNC
V_FB
R_FB1
GND
9
3448 F07
Figure 7. LTC3448 Layout Design
3448 F08
Figure 8. LTC3448 Layout
3448f
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