LTC3448_15 Datasheet, PDF (11/20 Pages) Linear Technology – 1.5MHz/2.25MHz, 600mA Synchronous Step-Down Regulator with LDO Mode

LTC3448
APPLICATIO S I FOR ATIO
worst, a sudden inrush of current through the long wires
can potentially cause a voltage spike at V_IN, large enough
to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Output Voltage Programming
The output voltage is set by tying V_FB to a resistive divider
according to the following formula:
V_OUT
=
⎛
0.6V _⎝⎜ 1+
R2^⎞
R1⎠⎟
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 5.
V_FB
LTC3448
GND
0.6V ≤ V_OUT ≤ 5.5V
R2
R1
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Figure 5. Setting the LTC3448 Output Voltage
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3448 circuits: V_IN quiescent current and I²R
losses. When in switching mode, V_IN quiescent current
loss dominates the efficiency loss at low load currents,
whereas the I²R loss dominates the efficiency loss at
medium to high load currents. At very low load currents
with the part operating in LDO mode, efficiency can be
dominated by I²R losses in the pass transistor and is a
strong function of (V_IN – V_OUT). In a typical efficiency plot,
the efficiency curve at very low load currents can be
misleading since the actual power lost is of little conse-
quence as illustrated in Figure 6.
1
V_IN = 3.6V
FREQ = 0V
LDOCNTRL = V_OUT(AUTO)
0.1
0.01
0.001
0.0001
0.0001
0.001
0.01
0.1
LOAD CURRENT (A)
1.2V
1.5V
1.8V
1
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Figure 6. Power Loss vs Load Current
1. The V_IN quiescent current is due to two components:
the DC bias current as given in the Electrical Character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V_IN to ground. The resulting
dQ/dt is the current out of V_IN that is typically larger than
the DC bias current and proportional to frequency. Both
the DC bias and gate charge losses are proportional to
V_IN and thus their effects will be more pronounced at
higher supply voltages.
2. I²R losses are calculated from the resistances of the
internal switches, R_SW, and external inductor R_L. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
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