LTC3421_15 Datasheet, PDF (13/16 Pages) Linear Technology – 3A, 3MHz Micropower Synchronous Boost Converter with Output Disconnect

LTC3421
APPLICATIO S I FOR ATIO
volts • seconds of the inductor will reverse during the time
current is flowing to the output. Since this mode will
dissipate more power in the IC, the maximum output
current is limited in order to maintain an acceptable
junction temperature.
( ) ( ) ^{IOUT(MAX) = 40 •}
125 – T_A
V_IN + 1.5 – V_OUT
where T_A = ambient temperature.
For example at V_IN = 4.5V and V_OUT = 3.3V, the maximum
output current is 370mA.
Short Circuit
The LTC3421 output disconnect feature allows output short
circuit while maintaining a maximum set current limit. The
IC has incorporated internal features such as current limit
and thermal shutdown for protection from an excessive
overload or short circuit. In applications that require a pro-
longed short circuit, it is recommended to limit the power
dissipation in the IC to maintain an acceptable junction
temperature. The circuit in Figure 2 will limit the maximum
current during a prolonged short by reducing the current
limit value in a short circuit by disconnecting R2 with the
N-channel MOSFET switch. R3 and C1 provide a soft-start
function after a short circuit. Resistor R1 lowers the cur-
rent limit value as V_IN rises, maintaining a relatively con-
stant power. The current limit equation for the circuit in
Figure 2 is given by:
I_LIMIT
=


0.6
R_LIM
–
V_IN – 0.6
R1


•
250
where I_LIMIT is in Amps; R_LIM and R1 are in kΩ.
TO V_IN
I_LIM
R1
8
1M
VN2222
R3
10k
TO V_OUT
R_LIM
100k
R2
C1
50k
0.1µF
3421 F02
Figure 2. Current Limit Foldback Circuit for
Extended Short Conditions
Closing the Feedback Loop
The LTC3421 uses current mode control with internal
adaptive slope compensation. Current mode control elimi-
nates the 2nd order filter due to the inductor and output
capacitor exhibited in voltage mode controllers, and sim-
plifies it to a single pole filter response. The product of the
modulator control to output DC gain and the error amp
open-loop gain gives the DC gain of the system:
G_DC
=
G_{CONTROL_OUTPUT}
•
G_EA
•
V_REF
V_OUT
G_CONTROL
=
2 • V_IN
I_OUT
,
G_EA
≈
2000
The output filter pole is given by:
f_{FILTER _ POLE}
=
π
•
I_OUT
V_OUT • C_OUT
where C_OUT is the output filter capacitor.
The output filter zero is given by:
f_{FILTER_ZERO}
=
2
•
π
1
• R_ESR
• C_OUT
where R_ESR is the capacitor equivalent series resistance.
A troublesome feature of the boost regulator topology is
the right-half plane zero (RHP) and is given by:
f_RHPZ
=
2
•
V_IN2
π • I_OUT
•L
At heavy loads this gain increase with phase lag can occur
at a relatively low frequency. The loop gain is typically
rolled off before the RHP zero frequency.
The typical error amp compensation is shown in Figure 3.
The equations for the loop dynamics are as follows:
f_POLE1
≈
2
•
π
•
1
20e6
•
C_C1
which
is
extremely
close
to
DC
f_ZERO1
≈
2•
π
1
•R_Z
• C_C1
f_POLE2
≈
1
2 • π •R_Z • C_C2
3421f
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