LTC2230 Datasheet, PDF (13/28 Pages) Linear Technology – Electrical Specifications Subject to Change

LTC2230/LTC2231
PI FU CTIO S
SENSE (Pin 59): Reference Programming Pin. Connecting
SENSE to V_CM selects the internal reference and a ±0.5V
input range. V_DD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±V_SENSE. ±1V is the largest valid input range.
V_CM (Pin 60): 1.6V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad): ADC Power Ground. The exposed
pad on the bottom of the package needs to be soldered to
ground.
(LVDS Mode)
AIN⁺ (Pins 1, 2): Positive Differential Analog Input.
AIN^– (Pins 3, 4): Negative Differential Analog Input.
REFHA (Pins 5, 6): ADC High Reference. Bypass to
Pins 7, 8 with 0.1µF ceramic chip capacitor, to Pins 11, 12
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5,
6 with 0.1µF ceramic chip capacitor. Do not connect to
Pins 11, 12.
REFHB (Pins 9, 10): ADC High Reference. Bypass to
Pins 11, 12 with 0.1µF ceramic chip capacitor. Do not
connect to Pins 5, 6.
REFLA (Pins 11, 12): ADC Low Reference. Bypass to
Pins 9, 10 with 0.1µF ceramic chip capacitor, to Pins 5, 6
with a 2.2µF ceramic capacitor and to ground with 1µF
ceramic capacitor.
V_DD (Pins 13, 14, 15, 62, 63): 3.3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.
GND (Pins 16, 61, 64): ADC Power Ground.
ENC⁺ (Pin 17): Encode Input. The input sample starts on
the positive edge.
ENC^– (Pin 18): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended ENCODE signal.
SHDN (Pin 19): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to V_DD results in normal operation with the
outputs at high impedance. Connecting SHDN to V_DD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V_DD and OE to V_DD
results in sleep mode with the outputs at high impedance.
OE (Pin 20): Output Enable Pin. Refer to SHDN pin
function.
DNC (Pins 21, 22, 23, 24): Do not connect these pins.
OGND (Pins 25, 33, 41, 50): Output Driver Ground.
OVDD (Pins 26, 34, 42, 49): Positive Supply for the
Output Drivers. Bypass to ground with 0.1µF ceramic chip
capacitor.
D0^–/D0⁺ to D9^–/D9⁺ (Pins 27 to 32, 37 to 40, 43 to 48, 51
to 54): LVDS Digital Outputs. All LVDS outputs require
differential 100Ω termination resistors at the LVDS re-
ceiver. D9^–/D9⁺ is the MBS.
CLKOUT^–/CLKOUT⁺ (Pins 35 to 36): LVDS Data Valid
Output. Latch data on rising edge of CLKOUT^–, falling edge
of CLKOUT⁺.
OF^–/OF⁺ (Pins 55 to 56): LVDS Over/Under Flow Output.
High when an over or under flow has occurred.
LVDS (Pin 57): Output Mode Selection Pin. Connecting
LVDS to 0V selects full rate CMOS mode. Connecting
LVDS to 1/3V_DD selects demux CMOS mode with simulta-
neous update. Connecting LVDS to 2/3V_DD selects demux
CMOS mode with interleaved update. Connecting LVDS to
V_DD selects LVDS mode.
MODE (Pin 58): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
straight binary output format and turns the clock duty
cycle stabilizer off. Connecting MODE to 1/3V_DD selects
straight binary output format and turns the clock duty
cycle stabilizer on. Connecting MODE to 2/3V_DD selects
2’s complement output format and turns the clock duty
cycle stabilizer on. Connecting MODE to V_DD selects 2’s
complement output format and turns the clock duty cycle
stabilizer off.
22301p
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