LTC2230 Datasheet, PDF (1/28 Pages) Linear Technology – Electrical Specifications Subject to Change

FEATURES
■ _{Sample Rate: 170Msps/135 Msps}
■ _{61dB SNR up to 140MHz Input}
■ _{75dB SFDR up to 200MHz Input}
■ _{775MHz Full Power Bandwidth S/H}
■ _{Single 3.3V Supply}
■ _{Low Power Dissipation: 890mW/660mW}
■ _{LVDS, CMOS, or Demultiplexed CMOS Outputs}
■ _{Selectable Input Ranges: ±0.5V or ±1V}
■ _{No Missing Codes}
■ _{Optional Clock Duty Cycle Stabilizer}
■ _{Shutdown and Nap Modes}
■ _{Data Ready Output Clock}
■ _{Pin Compatible Family}
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
■ _{64-Pin 9mm x 9mmQFN Package}
U
APPLICATIO S
■ _{Wireless and Wired Broadband Communication}
■ _{Cable Head-End Systems}
■ _{Power Amplifier Linearization}
■ _{Communications Test Equipment}
, LTC and LT are registered trademarks of Linear Technology Corporation.
Electrical Specifications Subject to Change
LTC2230/LTC2231
10-Bit,170Msps/
135Msps ADCs
DESCRIPTIO
The LTC^®2230 and LTC2231 are 170Msps/135Msps, sam-
pling 10-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2230/
LTC2231 are perfect for demanding communications
applications with AC performance that includes 61dB SNR
and 75dB spurious free dynamic range for signals
up to 200MHz. Ultralow jitter of 0.15ps_RMS allows
undersampling of IF frequencies with excellent noise
performance.
DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.12LSB_RMS.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data rate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.3V.
The ENC⁺ and ENC^– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
TYPICAL APPLICATIO
3.3V
V_DD
REFH
REFL
FLEXIBLE
REFERENCE
ANALOG
INPUT
+
INPUT
S/H
–
10-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
CLOCK/DUTY
CYCLE
CONTROL
ENCODE INPUT
OUTPUT
DRIVERS
0.5V
TO 3.3V
OV_DD
D9
•
•
•
D0
CMOS
OR
LVDS
OGND
22301 TA01
SFDR vs Input Frequency
90
85
80
75
70
65
60
55
50
45
40
0
4th OR HIGHER
2nd OR 3rd
100 200 300 400 500 600
INPUT FREQUENCY (MHz)
2230 TA01b
22301p
1