LTC3725 Datasheet, PDF (12/20 Pages) Linear Technology – Single-Switch Forward Controller and Gate Driver

LTC3725
APPLICATIO S I FOR ATIO
However, care should be taken to ensure that soft-start
transfer from primary-side to secondary-side is com-
pleted well before the output voltage reaches its target
value. A good design goal is to have the transfer completed
when the output voltage is less than one-half of its target
value. Note that the fastest output voltage rise time during
primary-side soft-start mode occurs with minimum load
current.
The open-loop start-up frequency on the LTC3725 is set
by placing a resistor R_FS(S) from the FS/IN^– pin to GND.
Although the exact start-up frequency on the primary side
is not critical, it is generally a good practice to set it
approximately equal to the operating frequency on the
secondary side.
In this mode the start-up frequency of the LTC3725 is
approximately:
f_PRI
=
34 • 10⁹
R_FS(S) + 10,000
In the event that the LTC3706 fails to start up properly and
assume control of switching, there are several fail-safe
mechanisms to help avoid overvoltage conditions. First,
the LTC3725 implements a volt-second clamp that may be
used to keep the primary-side duty cycle at a level that
does not produce an excessive output voltage. Second,
the timeout of the linear regulator (described in the follow-
ing section) means that, unless the LTC3706 starts and
supports the LTC3725 gate drive through the pulse trans-
former and on-chip rectifier, the LTC3725 eventually suf-
fers a gate drive undervoltage fault. Finally, the LTC3706
has an independent overvoltage detection circuit that
crowbars the output of the DC/DC converter using the
synchronous secondary-side MOSFET switch.
In the event that a short-circuit is applied to the output of
the converter prior to start-up, the LTC3706 generally
does not receive enough bias voltage to operate. In this
case, the LTC3725 detects a FAULT for one of two reasons:
1) since the LTC3706 never sends pulse encoding to the
LTC3725, the linear regulator times out resulting in a gate
drive undervoltage fault, or 2) the primary-side overcurrent
circuit is tripped because of current buildup in the output
inductor. In either case, the LTC3725 initiates a shutdown
followed by a soft-start retry.
Linear Regulator Timeout
After start-up, the LTC3725 times out the linear regulator
to prevent overheating of the external NMOS. The timeout
interval is set by further charging the soft-start capacitor
C_SSFLT from the end-of-soft-start voltage of approximately
2.8V to the timeout threshold of 3.9V. Linear regulator
timeout behaves differently depending on mode.
In primary-side standalone mode, the LTC3725 generally
requires that an auxiliary gate drive bias supply take over
from the linear regulator. (See the subsequent section for
more detail on the auxiliary supply.) During linear regula-
tor timeout, the rate of rise of the soft-start capacitor
voltage depends on the current into the NDRV pin as
controlled by the pull-up resistor R_PULLUP, the value of V_IN
and the value of V_NDRV.
I_NDRV
=
V_IN – V_NDRV
R_PULLUP
The value of V_NDRV is V_CC = 8V plus the value of the gate-
to-source voltage (V_NDRV – V_CC) of the external NMOS in
the linear regulator. The gate-to-source voltage depends
on the actual device but is approximately the threshold
voltage of the external NMOS.
For I_NDRV > 0.27mA, the capacitor on the SSFLT pin is
charged in proportion to (I_NDRV – 0.27mA) until the linear
regulator times out. Thus, since V_NDRV is very nearly
constant, the timeout interval for the linear regulator is
inversely proportional to the input voltage and a higher
input voltage produces a shorter timeout.
t_TIMEOUT
=
66C_SSFLT (3.9V – 2.8V)
⎡V_IN − V_NDRV
⎣⎢ ^RPULLUP
– 0.27mA^{⎤⎦⎥}
3725f
12