LTC3620 Datasheet, PDF (12/16 Pages) Linear Technology – Ultralow Power 15mA Synchronous Step-Down Switching Regulator

LTC3620
APPLICATIONS INFORMATION
A larger capacitor could be used to reduce this number.
Keep in mind that while a larger output capacitor will
decrease voltage ripple, it will also increase the transient
settling time. The optimal range for C_OUT should be be-
tween 1μF and 5μF.
The best way to select the feedback resistors is to select
a target combined resistance, and try different standard
1% resistor sizes to see which combination will give the
least error. For this example a target combined resistance
of around 1M will be used. By checking R1 values between
422k and 475k, and calculating R2 using the formula:
R2
=
(0.6V)R1
V_OUT – 0.6V
it can be found that a value of R2 = 523k and R1 = 432k
minimizes the error in this range.
The error can be checked by solving for V_OUT and find-
ing the percent error from the desired 1.1V. Using these
resistor values will result in V_OUT = 1.096V, and an error
of around 0.4%. Using different target resistor sums is
acceptable, but a smaller sum will decrease efficiency at
lower loads, and a larger sum will increase noise sensitiv-
ity at the V_FB pin.
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3620:
1. The power traces consisting of GND, SW and V_IN should
be kept short, direct and wide.
2. The V_FB pin should connect directly to the respective
feedback resistors, which should also have short, direct
paths to V_OUT and GND respectively.
3. Keep C_OUT and C_IN as close to the LTC3620 as
possible.
4. All parts connecting to ground should have their ground
terminals in close proximity to the LTC3620 GND
connection.
5. Keep the SW node and external clock, if used, away from
the sensitive V_FB node. Also, minimize the length and
area of all traces connected to the SW pin, and always
use a ground plane under the switching regulator to
minimize interplane coupling.
FMIN/MODE
LOBATB
C_OUT
L
V_IN
C_IN
SW 1
8 V_IN
GND 2
•
3
•••
•••
•••
7 RUN
6 V_FB
•
4
5 NC
R2 R1
C_FF*
FMIN/MODE
LOBATB
C_OUT
L
V_IN
C_IN
SW 1
GND 2
•
3
•
4
•••
•••
•••
8 V_IN
7 RUN
6 V_FB
5 NC
V_OUT
*C_FF = 22pF FEEDFORWARD CAPACITOR
3620 F04
LTC3620 Layout Diagram
V_OUT
3620 F05
LTC3620-1 Layout Diagram
3620f
12