LTC3620 Datasheet, PDF (10/16 Pages) Linear Technology – Ultralow Power 15mA Synchronous Step-Down Switching Regulator

LTC3620
APPLICATIONS INFORMATION
increase in switching losses internal to the part. This can
be partially offset by using inductors with lower loss.
The peak-to-peak output voltage ripple can be approxi-
mated by:
( ) _ΔV
=
(2 C_OUT
I_PK2 (L)(V_IN
)(V_OUT )(V_IN
)
–
V_OUT
)
The output ripple is a strong function of the peak inductor
current, I_PK. When the LTC3620 is locked to the minimum
switching frequency, I_PK is decreased to maintain regula-
tion. Consequently, ΔV_OUT is reduced in and below the
lock range.
Efficiency
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in the LTC3620’s circuits: V_IN quiescent current
and I²R losses. V_IN quiescent current loss dominates the
efficiency loss at low load currents, whereas the I²R loss
dominates the efficiency loss at medium to high load cur-
rents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of little consequence, as illustrated on the
front page of this data sheet.
The quiescent current is due to two components: the DC
bias current, I_Q, as given in the Electrical Characteristics,
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge, dQ, moves
from V_IN to ground. The resulting dQ/dt is the current out
of V_IN that is typically larger than the DC bias current and
proportional to frequency. Both the DC bias and gate charge
losses are proportional to V_IN and thus their effects will
be more pronounced at higher supply voltages.
The R_DS(ON) for both the top and bottom MOSFETS can
be obtained from the Typical Performance Characteristics
curves. The I²R losses per pulse will be proportional to
the peak current squared times the sum of the switch
resistance and the inductor resistance:
I²R
Loss
Pulse
=
I_PK ²
3
R_EFF
where R_EFF = R_L + R_PFET D + R_NFET (1 – D), and D is the
ratio of the top switch on-time to the total time of the pulse.
Additional losses incurred from the inductor DC resistance
and core loss may be significant in smaller inductors.
Capacitor Selection
Higher value, lower cost, ceramic capacitors are now
widely available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them
ideal for switching regulator applications. Because the
LTC3620’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
The output voltage ripple is inversely proportional to the
output capacitor. The larger the capacitor, the smaller the
ripple, and vice versa. However, the transient response
time is directly proportional to C_OUT, so a larger C_OUT
means slower response time.
To maintain stability and an acceptable output voltage
ripple, values for C_OUT should range from 1μF to 5μF.
3620f
10