LTC3538 Datasheet, PDF (12/16 Pages) Linear Technology – 800mA Synchronous Buck-Boost DC/DC Converter

LTC3538
OPERATION
1
FB
2
V_C
3
GND
4
BURST
8
V_IN
7
SW1
6
SW2
5
V_OUT
V_OUT
VIA TO GND PLANE
3538 F03
Figure 3. LTC3538 Recommended PCB Layout
Closing the Feedback Loop
The LTC3538 incorporates voltage mode PWM control.
The control to output gain varies with operation region
(buck, boost, buck-boost), but is usually no greater than
15. The output filter exhibits a double pole response, as
given by:
ƒ_{FILTER _POLE} = _{2• π •}
1
Hz
L • C_OUT
(in buck mode)
ƒ_FILTER
_ POLE
=
2
•
V_OUT
•
V_IN
π•
Hz
L • C_OUT
(in boost mode)
where L is in Henries and C_OUT is in Farads.
The output filter zero is given by:
ƒ_FILTER
_
ZERO
=
2•
π
•
1
R_ESR
•
C_OUT
Hz
where R_ESR is the equivalent series resistance of the
output capacitor.
A troublesome feature in boost mode is the right-half plane
zero (RHP), given by:
ƒ_RHPZ
=
2•π
V_IN2
•I_OUT •L •
V_OUT
Hz
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network can be incorporated
to stabilize the loop, but at a cost of reduced bandwidth and
slower transient response. To ensure proper phase margin
using Type I compensation, the loop must be crossed
over a decade before the LC double pole. Referring to
Figure 4, the unity-gain frequency of the error amplifier
with the Type I compensation is given by:
ƒ_UG
=
2
•
π
•
1
R1•
C_P1
Hz
1V
FB
1
V_OUT
R1
V_C
C_P1
2
R2
3538 F04
Figure 4. Error Amplifier with Type I Compensation
3538fb
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