LTC3419 Datasheet, PDF (12/16 Pages) Linear Technology – Dual Monolithic 600mA Synchronous Step-Down Regulator

LTC3419
APPLICATIONS INFORMATION
The R_DS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I²R losses:
I²R losses = I_OUT2 • (R_SW + R_L)
4. Other “hidden” losses, such as copper trace and internal
battery resistances, can account for additional efficiency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C_IN has adequate
charge storage and very low ESR at the switching fre-
quency. Other losses, including diode conduction losses
during dead-time, and inductor core losses, generally
account for less than 2% total additional loss.
Thermal Considerations
In a majority of applications, the LTC3419 does not dis-
sipate much heat due to its high efficiency. In the unlikely
event that the junction temperature somehow reaches ap-
proximately 150°C, both power switches will be turned off
and the SW node will become high impedance. The goal
of the following thermal analysis is to determine whether
the power dissipated causes enough temperature rise to
exceed the maximum junction temperature (125°C) of the
part. The temperature rise is given by:
T_RISE = P_D • θ_JA
Where P_D is the power dissipated by the regulator and
θ_JA is the thermal resistance from the junction of the die
to the ambient temperature. The junction temperature,
T_J, is given by:
T_J = T_RISE + T_AMBIENT
As a worst-case example, consider the case when the
LTC3419 is in dropout on both channels at an input volt-
age of 2.7V with a load current of 600mA and an ambi-
ent temperature of 70°C. From the Typical Performance
Characteristics graph of Switch Resistance, the R_DS(ON)
of the main switch is 0.6Ω. Therefore, power dissipated
by each channel is:
P_D = I_OUT2 • R_DS(ON) = 216mV
Given that the thermal resistance of a properly soldered
DFN package is approximately 40°C/W, the junction
temperature of an LTC3419 device operating in a 70°C
ambient temperature is approximately:
T_J = (2 • 0.216W • 40°C/W) + 70°C = 87.3°C
which is well below the absolute maximum junction tem-
perature of 125°C.
PC Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3419. These items are also illustrated graphically
in the layout diagrams of Figures 2 and 3. Check the fol-
lowing in your layout:
1. Does the capacitor C_IN connect to the power V_IN (Pin 5)
and GND (Pin 9) as closely as possible? This capacitor
provides the AC current of the internal power MOSFETs
and their drivers.
2. Are the respective C_OUT and L closely connected? The
(–) plate of C_OUT returns current to GND and the (–)
plate of C_IN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C_OUT1 and a ground sense line
terminated near GND (Pin 9). The feedback signals V_FB1
and V_FB2 should be routed away from noisy components
and traces, such as the SW lines (Pins 4 and 6), and
their trace length should be minimized.
4. Keep sensitive components away from the SW pins, if
possible. The input capacitor C_IN and the resistors R1,
R2, R3 and R4 should be routed away from the SW
traces and the inductors.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the GND pin at a single
point. These ground traces should not share the high
current path of C_IN or C_OUT.
6. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components. These copper areas should be
connected to V_IN or GND.
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