LTC3418 Datasheet, PDF (12/20 Pages) Linear Technology – 8A, 4MHz, Monolithic Synchronous Step-Down Regulator

LTC3418
APPLICATIO S I FOR ATIO
The output voltage during tracking can be calculated with
the following equation:
V_OUT = V_TRACK^{⎛⎝⎜}1+ ^{RR21⎞⎠⎟} ,V_TRACK < 0.8V
To implement the coincident tracking in Figure 2a, con-
nect an extra resistor divider to the output of V_OUT2 and
connect its midpoint to the TRACK pin of the LTC3418 as
shown in Figure 3a. The ratio of this divider should be
selected the same as that of V_OUT1’s resistor divider. To
implement the ratiometric sequencing in Figure 2b, no
extra resistor divider is necessary. Simply connect the
TRACK pin to V_FB2, as shown in Figure 3b.
V_OUT2
(MASTER)
TRACK
PIN
R2 R4
V_FB(MASTER)
PIN
R1 R3
TRACK
PIN
V_OUT2
(MASTER)
R2
V_FB(MASTER)
R1
(3a) Coincident Setup
Figure 3
3418 F03
(3b) Ratiometric Setup
Frequency Synchronization
The LTC3418’s internal oscillator can be synchronized to
an external clock signal. During synchronization, the top
MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set by
the external resistor. Because slope compensation is
generated by the oscillator’s RC circuit, the external fre-
quency should be set 25% higher than the frequency set
by the external resistor to ensure that adequate slope
compensation is present.
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3418 as well as a timer for soft-start. Pulling the RUN/
SS pin below 0.5V places the LTC3418 in a low quiescent
current shutdown state (I_Q < 1.5µA).
The LTC3418 contains a soft-start clamp that can be set
externally with a resistor and capacitor on the RUN/SS pin
as shown in Typical Application on the front page of this
data sheet. The soft-start duration can be calculated by
using the following formula:
[ ] ^tSS
= R_SS
• C_SS
• In ^VIN
V_IN – 1.8V
Seconds
When the voltage on the RUN/SS pin is raised above 2V,
the full current range becomes available on I_TH.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V_IN quiescent current and I²R losses.
The V_IN quiescent current loss dominates the efficiency
loss at very low load currents whereas the I²R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The V_IN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from V_IN to ground. The resulting dQ/dt is the current out
of V_IN that is typically larger than the DC bias current. In
continuous mode, I_GATECHG = f(Q_T + Q_B) where Q_T and Q_B
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V_IN and thus their effects will be more
pronounced at higher supply voltages.
3418f
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