LTC3371_15 Datasheet, PDF (12/26 Pages) Linear Technology – 4-Channel 8A Configurable Buck DC/DCs with Watchdog and Power-On Reset

LTC3371
Pin Functions (QFN/TSSOP)
FB1 (Pin 1/Pin 5): Buck Regulator 1 Feedback Pin. Receives
feedback by a resistor divider connected across the output.
V_INA (Pin 2/Pin 6): Power Stage A Input Supply. Bypass
to GND with a 10µF or larger ceramic capacitor.
SWA (Pin 3/Pin 7): Power Stage A Switch Node. External
inductor connects to this pin.
SWB (Pin 4/Pin 8): Power Stage B Switch Node. External
inductor connects to this pin.
V_INB (Pin 5/Pin 9): Power Stage B Input Supply. Bypass
to GND with a 10µF or larger ceramic capacitor.
V_INC (Pin 6/Pin 10): Power Stage C Input Supply. Bypass
to GND with a 10µF or larger ceramic capacitor.
SWC (Pin 7/Pin 11): Power Stage C Switch Node. External
inductor connects to this pin.
SWD (Pin 8/Pin 12): Power Stage D Switch Node. External
inductor connects to this pin.
V_IND (Pin 9/Pin 13): Power Stage D Input Supply. Bypass
to GND with a 10µF or larger ceramic capacitor.
FB2 (Pin 10/Pin 14): Buck Regulator 2 Feedback Pin.
Receives feedback by a resistor divider connected across
the output. In configurations where Buck 2 is not used,
FB2 should be tied to ground.
EN2 (Pin 11/Pin 15): Buck Regulator 2 Enable Input.
Active high. In configurations where Buck 2 is not used,
tie EN2 to ground. Do not float.
RST2 (Pin 12/Pin 16): Buck Regulator 2 Reset Pin
(Active Low). Open-drain output. When Buck 2 is disabled
or its regulated output voltage is more than 5% below its
programmed level, this pin is driven low. Assertion delay
is scaled by the C_T capacitor.
C1 (Pin 13/Pin 17): Configuration Control Input Bit. With
C2 and C3, C1 configures the Buck output current power
stage combinations. C1 should either be tied to V_CC or
ground. Do not float.
C2 (Pin 14/Pin 18): Configuration Control Input Bit. With
C1 and C3, C2 configures the Buck output current power
stage combinations. C2 should either be tied to V_CC or
ground. Do not float.
C3 (Pin 15/Pin 19): Configuration Control Input Bit. With
C1 and C2, C3 configures the Buck output current power
stage combinations. C3 should either be tied to V_CC or
ground. Do not float.
WDI (Pin 16/Pin 20): Watchdog Timer Input. The WDI pin
must be toggled either low to high or high to low every
1.62 seconds. Failure to toggle WDI results in the WDO
pin being pulled low for 202ms. All times correspond to
a 10nF capacitor on the CT pin.
WDO (Pin 17/Pin 21): Watchdog Timer Output. Open-drain
output. WDO is pulled low for 202ms during a watchdog
timeout period. The WDO pin pulls low if the WDI input
does not transition in less than 1.62 seconds since its last
transition or 12.9 seconds after a watchdog timeout period.
A V_CC UVLO event resets the watchdog timer and WDO
asserts itself low for the 202ms watchdog timeout period.
All times correspond to a 10nF capacitor on the CT pin.
CT (Pin 18/Pin 22): Timing Capacitor Pin. A capacitor
connected to GND sets a time constant which is scaled
for use by the WDI, WDO, and RST1-4 pins.
RST3 (Pin 19/Pin 23): Buck Regulator 3 Reset Pin
(Active Low). Open-drain output. When Buck 3 is disabled
or its regulated output voltage is more than 5% below its
programmed level, this pin is driven low. Assertion delay
is scaled by the C_T capacitor.
EN3 (Pin 20/Pin 24): Buck Regulator 3 Enable Input.
Active high. In configurations where Buck 3 is not used,
tie EN3 to ground. Do not float.
FB3 (Pin 21/Pin 25): Buck Regulator 3 Feedback Pin.
Receives feedback by a resistor divider connected across
the output. In configurations where Buck 3 is not used,
FB3 should be tied to ground.
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