LT1113 Datasheet, PDF (12/16 Pages) Linear Technology – Dual Low Noise, Precision, JFET Input Op Amps

LT1113
APPLICATI
15V
IN^{– 3} +
8
1/2
1
LT1113
2 _– IC1
4
–15V
S I FOR ATIO
R4
R6
1k
10k
C1
R1
50pF
1k
R2
200Ω
2–
1/2
LT1113
3 + IC2
R3
6–
1k
R5
1/2
7
LT1113
IN^{+ 5 + IC1}
1k
R7
10k
GAIN = 100
BANDWIDTH = 400kHz
INPUT REFERRED NOISE = 6.6nV/√Hz AT 1kHz
WIDEBAND NOISE DC TO 400kHz = 6.6 µV_RMS
C_L ≤ 0.01µF
1
OUTPUT
C_L
1113 • F04
Figure 4. Three Op Amp Instrumentation Amplifier
The concepts of common mode and power supply
rejection ratio match (∆CMRR and ∆PSRR) are best
demonstrated with a numerical example:
Assume CMRR_A = +50µV/V or 86dB,
and CMRR_B = + 39µV/V or 88dB,
then ∆CMRR = 11µV/V or 99dB;
if CMRR_B = -39µV/V which is still 88dB,
then ∆CMRR = 89µV/V or 81dB
Clearly the LT1113, by specifying and guaranteeing all of
these matching parameters, can significantly improve the
performance of matching-dependent circuits.
Typical performance of the instrumentation amplifier:
Input offset voltage = 0.8mV
Input bias current = 320pA
Input offset current = 10pA
Input resistance = 10¹¹â„¦
Input noise = 3.4µV_P-P
High Speed Operation
The low noise performance of the LT1113 was achieved by
making the input JFET differential pair large to maximize
the first stage gain. Increasing the JFET geometry also
increases the parasitic gate capacitance, which if left
unchecked, can result in increased overshoot and ringing.
When the feedback around the op amp is resistive (R_F),
a pole will be created with R_F, the source resistance and
capacitance (R_S,C_S), and the amplifier input capacitance
(C_IN = 27pF). In closed loop gain configurations and
with R_S and R_F in the kilohm range (Figure 5), this pole
can create excess phase shift and even oscillation.
A small capacitor (C_F) in parallel with R_F eliminates this
problem. With R_S(C_S + C_IN) = R_FC_F, the effect of the
feedback pole is completely removed.
C_F
R_S
C_S
R_F
–
+ ^CIN
Figure 5.
OUTPUT
1113 • F05
12