LTC3785-1 Datasheet, PDF (11/20 Pages) Linear Technology – 10V, High Effi ciency, Buck-Boost Controller with Power Good

LTC3785-1
OPERATION
of the voltage loop, resulting in a lower output voltage
to regulate the input current. This fault condition causes
the RUN/SS capacitor to begin discharging. The level of
the discharge current depends on how much the current
exceeds the programmed threshold. Figure 3 is a simpli-
fied diagram of the current sense and fault circuitry. If the
current limit fault duration is long enough to discharge the
RUN/SS capacitor below 1.225V, the fault latch is set and
will cycle the RUN/SS capacitor 16 times (1μA charging
and 1μA discharging of the RUN/SS capacitor) to create an
off time of 32 times the soft-start time before the outputs
are allowed to switch to restart the output voltage. If the
current limit fault level exceeds 150% of the programmed
I_LIMIT level at any time, the I_MAX comparator is tripped and
output switches B and D are turned on to discharge the
inductor current for the remainder of the cycle.
To have the power converter latch-off on a fault, a pull-up
current between 4μA and 7μA on the RUN/SS pin will allow
the RUN/SS capacitor to discharge during an extended
fault, but will prevent cycling of the fault which will cause the
converter to stay off. One method to implement this is by
placing a diode (anode tied to V_OUT) and a resistor from V_OUT
to the RUN/SS pin. The current sourced into RUN/SS will be
V_OUT – 0.7 divided by the resistor value. To ignore all faults
source greater than 40μA into the RUN/SS pin (At 1.225V on
the RUN/SS pin). Since the maximum fault current is limited,
this will prevent any discharging of the RUN/SS capacitor,
the soft-start capacitor will need to be sized accordingly to
accommodate the extra charging current at start-up.
During an output short-circuit or if V_OUT is less than 1.8V, the
current limit folds back to 50% of the programmed level.
REVERSE CURRENT LIMIT
The LTC3785-1 can be programmed to provide full class
D operation or allowed to source and sink current equal to
the current limit set value. This is achieved by asserting a
high level on the CCM pin. To minimize the reverse output
current, the CCM pin should be driven low or strapped to
ground. During this mode only, –15mV typical is allowed
across output switch D and is sensed with the I_SVOUT and
I_SSW2 pins.
THERMAL SD
1.225V +
–
–
0.7V
+
S FAULT
S LOGIC
RUN
g_m = 1/20k
I_LIMIT COMP
g_m
V = 60k/R_ILSET
(15k/R_ILSET WHEN V_OUT < 1.8V)
I_SVIN
22
TG1 20
RUN/SS
1
C_SS
4
V_OUT
R1
FB
3
C_P1
V_C
2
R2
I_LSET
5
R_ILSET
1μA
2.2V
2μA
1/3 • I_LIM(OUT)
10μA MAX
I_LIM(OUT)
30μA MAX
1.225V
+ ^{ERROR AMP}
–
I_LIMIT
SET
I_LIM COMP
I_MAX COMP
I_MAX COMP
TURN
SWITCHES
B AND D ON
V = 90k/R_ILSET
SW1 19
X10
I_SSW1
SAMPLED
18
BG1 17
CCM = HIGH = 6k/R_ILSET
CCM = LOW = 15mV
CCM
6
SWITCH D
OFF
REVERSE
CURRENT LIMIT
–+
I_SVOUT
10
TG2 12
SW2 13
SAMPLED ^ISSW2 14
BG2 15
Figure 3. Block Diagram of Current Limit Fault Circuitry
V_IN
A
B
L1
V_OUT
D
C_OUT
C
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