LTC3564_15 Datasheet, PDF (11/20 Pages) Linear Technology – 2.25MHz, 1.25A Synchronous Step-Down Regulator

LTC3564
APPLICATIO S I FOR ATIO
Output Voltage Programming
In the adjustable version, the output voltage is set by a
resistive divider according to the following formula:
V_OUT = 0.6V^{⎛⎝⎜}1+ ^{RR21⎞⎠⎟}
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 2.
V_FB
LTC3564
GND
0.6V ≤ V_OUT ≤ 5.5V
R2
R1
3564 F02
Figure 2. Setting the LTC3564 Output Voltage
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3564 circuits: V_IN quiescent current and I²R
losses. The V_IN quiescent current loss dominates the
efficiency loss at very low load currents whereas the I²R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 3.
1
V_IN = 3.6V
0.1
0.01
0.001
0.0001
0.1
V_OUT = 1.2V
V_OUT = 1.5V
V_OUT = 1.8V
1
10 100 1000 10000
LOAD CURRENT (A)
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Figure 3. Power Lost vs Load Current
1. The V_IN quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V_IN to ground. The resulting
dQ/dt is the current out of V_IN that is typically larger than
the DC bias current. In continuous mode, I_GATECHG =
f(Q_T + Q_B) where Q_T and Q_B are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V_IN and thus
their effects will be more pronounced at higher supply
voltages.
2. I²R losses are calculated from the resistances of the
internal switches, R_SW, and external inductor R_L. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R_DS(ON) and the duty cycle
(DC) as follows:
R_SW = (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)
3564f
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