LT1619_15 Datasheet, PDF (11/20 Pages) Linear Technology – Low Voltage Current Mode PWM Controller

LT1619
APPLICATIO S I FOR ATIO
Here the input voltage ripple is filtered with R3, R4 and C1
so as to prevent the input ripple from falsely tripping the
LT1619 synchronization circuit. It is recommended that:
R4 ≈ ^1R3
5
( ) ^and
1
<< f_OSC
2π R3 || R4 C1
Implementation of Hysteretic UVLO
with External Synchronization
The UVLO circuit shown in Figure 10 operates down to
0.9V supply voltage. Algebraically the UVLO trip points
are:
V_INH
=
V_Z
+

V_{BE } 1+
R5 ^
R6 ||R7
and
( ) ^{R5 || R7 + R9}
( ) ^{ R5 || R7 + R9 }
V_INL =
R5
( ) ^{VZ + VBE}_{} ^{R5 ||R6 || R7 + R9} _{}
UVLO Hysteresis
=
V_INH
–
V_INL
=

 R5
+
R5
R7
+

R9
V_Z
+
( ) _VBE


R5
R6 ||R7
–
R5 ||
R7 + R9
R6


The collector votage of Q2 is made about 1.4V at the V_IN
lower trip voltage. This is necessary to prevent the UVLO
circuit from interfering with the feedback amplifier in the
LT1619.
Trickle Current Start from High Voltage Supplies
The low shutdown and idle mode quiescent supply cur-
rents of the LT1619 can be utilized to implement trickle
current start from high voltage input sources (such as a
36V to 72V telecom bus). The trickle current start-up
circuit in Figure 11 is modified from the UVLO circuit of
Figure 10. R10 is a high value resistor that charges the
storage capacitor C2 during start-up. Before V_CC reaches
the upper UVLO trip point, Q2 holds the S/S pin low. The
LT1619 draws shutdown mode current (≈15µA) from V_CC.
Q2 collector can also be tied to the V_C pin through a diode
as in Figure 10. The LT1619 will then draw idle mode
quiescent current (≈140µA) from V_CC. R10 should be able
to charge C2 while supplying current to the UVLO circuit
and the LT1619. Maximizing R5 to R9 values reduces
power dissipation in R10.
When V_CC crosses the upper UVLO threshold, the LT1619
starts switching and its current consumption increases.
Before the bootstrap takes over, the LT1619 draws its
current from C2. V_CC ramps towards the lower UVLO
threshold. Increasing the value of C2 allows more time for
the bootstrap circuit to establish itself before the converter
enters undervoltage lockout.
V_IN
+
8.2V _–
R5
51k
R6
51k
R8
R9
30k
510k
R7
51k
CLK
D1
BAT85
Q1
2N2222
Q2
2N2222
1
S/S
8
V_IN
2
FB
7
DRV
LT1619
3
6
V_C
GATE
4
GND
5
SENSE
1619 F10
V_IN UPPER TRIP POINT = 10V
V_IN LOWER TRIP POINT = 8.4V
Figure 10. Addition of Hysteresis UVLO While Synchronizing the
LT1619. Component Values Shown are for the Upper and the
Lower V_IN Trip Points of 10V and 8.4V. In UVLO, the Gate Drive
is Disabled by Pulling the V_C Pin Low. Disabling the Clock Shuts
Down the LT1619. If Not Synchronized, the Collector of Q2 Can
Be Tied to the S/S Pin and the Diode D1 Can Be Eliminated
HV V_IN
R10
V_CC
C2
R5
R6
R8
R9
R7
Q2
Q1
1
S/S
8
V_IN
2
FB
7
DRV
LT1619
3
6
V_C
GATE
4
GND
5
SENSE
1619 F11
BOOTSTRAP
WINDING
D2
T1
Figure 11. Trickle Current Start-Up with Bootstrapped V_CC
1619fa
11