LT1619_15 Datasheet, PDF (10/20 Pages) Linear Technology – Low Voltage Current Mode PWM Controller

LT1619
APPLICATIO S I FOR ATIO
f_CORNER
=
1
2πR_OSC_S
≈
5f_S
(The input impedance of the sense amplifier at the SENSE
pin is 2500Ω and R_OS is typically less than 137Ω.) Typical
values for R_OS and C_S are 100Ω and 1nF. The 100Ω value
for R_OS reduces Burst Mode threshold; use 10Ω and 10nF
when this is not desireable.
V_IN
V_Z
R3
1
S/S
8
V_IN
I_{S/S 2}
FB
7
DRV
LT1619
3
6
V_C
GATE
4
GND
5
SENSE
1619 F07
( ) IS/S
V_S/S = 0
R3 < SHUTDOWN THRESHOLD
UVLO THRESHOLD = V_Z + SHUTDOWN
THRESHOLD ≈ V_Z + V_BE
I_S/S
≈ –2µA
V_S/S = 0
PWM
COMPARATOR
LT1619
CURRENT
SENSE
AMPLIFIER
I_D
SENSE
5
GND
4
R_OS
C_{S RSENSE}
+
V_SENSE
–
1619 F06
Figure 7. Implementing Undervoltage Lockout
I
+
I
V
–
ZENER
DIODE
AVALANCHE
DIODE
Figure 6. Current Sense Filter for Improving Jitter Performance
Use of Shutdown Function to
Modify Undervoltage Lockout
The LT1619 is designed to operate from an input supply
with voltage as low as 1.85V. Shutdown is activated when
the S/S pin is pulled below 0.45V. The shutdown threshold
is slightly greater than one junction diode forward voltage
and has the temperature characteristics of a junction
diode. The S/S pin is normally tied to the input when
operating from a low voltage input source.
Consider the 12V to – 65V isolated flyback converter (see
Typical Applications). The converter draws 3A at low line
while delivering 0.4A to the output. If the S/S pin is tied to
the input, then the LT1619 will start switching as soon as
V_IN exceeds the internal UVLO threshold. With full load,
the converter can draw much higher than the steady-state
3A from the input source during start-up. If the input
source is current limited, the input voltage will collapse
and latch low.
The start-up problem can be prevented by adding a zener
diode and a resistor to the S/S pin (Figure 7). This is
equivalent to increasing undervoltage lockout voltage of
the controller. Before V_IN exceeds the zener voltage V_Z, the
S/S pin current is shunted to the ground through the
10
V
0
BV < 5V
Figure 8. I-V Characteristics of Zener
and Avalanche Breakdown Diodes
V_IN
R4
1
S/S
8
V_IN
2
FB
7
DRV
C1
R3
LT1619
3
6
V_C
GATE
4
GND
5
SENSE
1619 F09
Figure 9. Filtering Input Voltage Ripple in UVLO Circuit
resistor R3. The voltage developed across R3 due to I_S/S
should be less than the shutdown threshold. The LT1619
remains off until V_IN exceeds the sum of V_Z and the
shutdown threshold. True zener diodes (BV < 5V) and
higher voltage avalanche diodes have different I-V charac-
teristics (Figure 8). They need to be biased appropriately
(value of R3) in order to obtain correct UVLO threshold.
When implementing UVLO with converters with high input
ripple voltages (such as flyback and forward), the circuit
in Figure 7 is modified and shown in Figure 9.
1619fa