LTC1662_15 Datasheet, PDF (10/16 Pages) Linear Technology – Ultralow Power, Dual 10-Bit DAC in MSOP

LTC1662
Operation
The first of these, the input register, is used for loading
new input codes. The second buffer, the DAC register, is
used for updating the DAC outputs. Each DAC has its own
10‑bit input register and 10-bit DAC register.
By selecting the appropriate 4-bit control code (see Table 1)
it is possible to perform single operations, such as loading
one DAC or changing power-down status (sleep/wake).
In addition, some control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and Wakes the part
up. The DACs can be loaded separately or together, but
the outputs are always updated together.
Register Loading Sequence
See Figure 1. With CS/LD held low, data on the SDI input
is shifted into the 16-bit shift register on the positive edge
of SCK. The 4-bit control code, A3-A0, is loaded first, then
the 10-bit input code, D9-D0, ordered MSB to LSB in each
case. Two don’t-care bits, X1 and X0, are loaded last. When
the full 16-bit input word has been shifted in, CS/LD is
pulled high, causing the system to respond according to
Table 1. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
Sleep Mode
DAC control code 1110_b is reserved for the special sleep
instruction (see Table 1). In this mode, static power
consumption is greatly reduced. The reference input and
analog outputs are set in a high impedance state and all
DAC settings are retained in memory so that when sleep
mode is exited, the outputs of DACs not updated by the
Wake command are restored to their last active state.
Sleep mode is initiated by performing a load sequence
using control code 1110_b (the DAC input code D9-D0 is
ignored).
To save instruction cycles, the DACs may be prepared
with new input codes during sleep (control codes 0001_b
and 0010_b); then, a single command (1000_b) can be used
both to wake the part and to update the output values.
Alternatively, one DAC may be loaded with a new input
code during sleep; then with just one command, the other
DAC is loaded, the part is awakened and both outputs are
updated.
For example, control code 0001_b is used to load DAC A
during sleep. Then control code 0101_b loads DAC B, wakes
the part and simultaneously updates both DAC outputs.
Voltage Outputs
Each of the rail-to-rail output amplifiers contained in
the LTC1662 can typically source or sink at least 1mA
(V_CC = 5V). The outputs swing to within a few millivolts
of either supply when unloaded and have an equivalent
output resistance of 130Ω (typical) when driving a load to
the rails. The output amplifiers are stable driving capacitive
loads of up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. Please
see the Output Minimum Resistance vs Load Capacitance
curve in the Typical Performance Characteristics section.
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to volt-
ages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full-scale when the REF
pin is tied to V_CC. If V_REF = V_CC and the DAC full-scale error
(FSE = V_OS + GE) is positive, the output for the highest
codes limits at V_CC as shown in Figure 2c. No full-scale
limiting can occur if V_REF is less than V_CC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
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