LT1113_15 Datasheet, PDF (10/16 Pages) Linear Technology – Dual Low Noise, Precision, JFET Input Op Amp

LT1113
APPLICATI
S I FOR ATIO
R2
C_B
R_B
–
R1
+
OUTPUT
C_S R_S
C_B ≅ C_S
R_B = R_S
R_S > R1 OR R2
TRANSDUCER
C_S R_S
R_F
C_F
–
+
OUTPUT
TRANSDUCER
C_B
R_B
C_B = C_FC_S
R_B = R_FR_S
Q = CV;_{dd}^Qt = I = C_^dd_^Vt
1113 • F02
Figure 2. Noninverting and Inverting Gain Configurations
The gain therefore is 1 + C_F/C_S. For unity gain, C_F should
equal the transducer capacitance plus the input capaci-
tance of the LT1113 and R_F should equal R_S. In the
noninverting mode example, the transducer current is
converted to a change in voltage by the transducer capaci-
tance; this voltage is then buffered by the LT1113 with a
gain of 1 + R1/R2. A DC path is provided by R_S, which is
either the transducer impedance or an external resistor.
Since R_S is usually several orders of magnitude greater
than the parallel combination of R1 and R2, R_B is added to
balance the DC offset caused by the noninverting input
bias current and R_S. The input bias currents, although
small at room temperature, can create significant errors
over increasing temperature, especially with transducer
resistances of up to 100M or more. The optimum value for
R_B is determined by equating the thermal noise (4kTR_S) to
the current noise (2qI_B) times R_S2. Solving for R_S results
in R_B = R_S = 2V_T/I_B

 ^VT
=
kT
q
=
26mV
at

25°C_.
A parallel capacitor, C_B, is used to cancel the phase shift
caused by the op amp input capacitance and R_B.
Reduced Power Supply Operation
The LT1113 can be operated from ±5V supplies for lower
power dissipation resulting in lower I_B and noise at the
expense of reduced dynamic range. To illustrate this
benefit, let’s look at the following example:
An LT1113CS8 operates at an ambient temperature of
25°C with ±15V supplies, dissipating 318mW of power
(typical supply current = 10.6mA for the dual). The SO-8
package has a θ_JA of 190°C/W, which results in a die
temperature increase of 60.4°C or a room temperature die
operating temperature of 85.4°C. At ±5V supplies, the die
temperature increases by only one third of the previous
amount or 20.1°C resulting in a typical die operating
temperature of only 45.1°C. A 40 degree reduction of die
temperature is achieved at the expense of a 20V reduction
in dynamic range. If no DC correction resistor is used at
the input, the input referred offset will be the input bias
current at the operating die temperature times the trans-
ducer resistance (refer to Input Bias and Offset Currents vs
Chip Temperature graph in Typical Performance Charac-
teristics section). A 100mV input V_OS is the result of a 1nA
I_B (at 85°C) dropped across a 100M transducer resis-
tance; at ±5V supplies, the input offset is only 28mV (I_B at
45°C is 280pA). Careful selection of a DC correction
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