LTM9012_15 Datasheet, PDF (1/28 Pages) Linear Technology – Quad 14-Bit, 125Msps ADC with Integrated Drivers

LTM9012
Quad 14-Bit, 125Msps ADC
with Integrated Drivers
Features
n _{4-Channel Simultaneous Sampling ADC with}
Integrated, Fixed Gain, Differential Drivers
n _{68.3dB SNR}
n _{78dB SFDR}
n _{Low Power: 1.27W Total, 318mW per Channel}
n _{1.8V ADC Core and 3.3V Analog Input Supply}
n _{Serial LVDS Outputs: 1 or 2 Bits per Channel}
n _{Shutdown and Nap Modes}
n _{11.25mm × 15mm BGA Package}
Applications
n _{Industrial Imaging}
n _{Medical Imaging}
n _{Multichannel Data Acquisition}
n _{Nondestructive Testing}
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
Description
The LTM^®9012 is a 4-channel, simultaneous sampling
14-bit µModule^® analog-to-digital converter (ADC) with
integrated, fixed gain, differential ADC drivers. The low
noise amplifiers are suitable for single-ended drive and
pulse train signals such as imaging applications. Each
channel includes a lowpass filter between the driver out-
put and ADC input.
DC specs include ±1.2LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 1.2LSB_RMS.
The digital outputs are serial LVDS and each channel out-
puts two bits at a time (2-lane mode). At lower sampling
rates there is a one bit option (1-lane mode). The LVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
The ENC⁺ and ENC^– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
Typical Application
Single-Ended Sensor Digitization
3.3V
1.8V
1.8V
IMAGE
SENSOR
V_REF
V_CC
V_DD
OV_DD
LTM9012
PIPELINE ¹⁴
ADC
DATA
SERIALIZER
CHANNEL 1
ENCODER
•
•
PIPELINE ¹⁴
ADC
AND
LVDS
DRIVERS
CHANNEL 2
•
PIPELINE ¹⁴
CHANNEL 3
ADC
PIPELINE ¹⁴
ADC
INTERNAL
REFERENCE & SUPPLY
BYPASS CAPACITORS
SCK SDI SDO CS PAR/SER
PLL
ENC⁺
CHANNEL 4
ENC^–
FR⁺
FR^–
DCO⁺
DCO^–
FPGA
ENCODE CLOCK
9012 TA01a
LTM9012, 125Msps, 70MHz FFT
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30 35 40 45 50 55 60
FREQUENCY (MHz)
9012 TA01b
9012f
1