LTC2654 Datasheet, PDF (1/24 Pages) Linear Technology – Quad 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference

FEATURES
n _{Precision Reference 10ppm/°C Max}
n _{Maximum INL Error: ±4LSB at 16-Bits}
n _{Low ±2mV (Max) Offset Error}
n _{Guaranteed Monotonic Over Temperature}
n _{Selectable Internal or External Reference}
n _{2.7V to 5.5V Supply Range (LTC2654-L)}
n _{Integrated Reference Buffers}
n _{Ultralow Crosstalk Between DACs (<3nV•s)}
n _{Power-on-Reset to Zero-Scale/Mid-Scale}
n _{Asynchronous DAC Update Pin}
n _{Tiny 20-Lead 4mm × 4mm QFN and 16-Lead Narrow}
SSOP Packages
APPLICATIONS
n _{Mobile Communications}
n _{Process Control and Industrial Automation}
n _{Instrumentation}
n _{Automatic Test Equipment}
n _Automotive
LTC2654
Quad 16-/12-Bit Rail-to-Rail
DACs with 10ppm/°C
Max Reference
DESCRIPTION
The LTC^®2654 is a family of quad 16-/12-bit rail-to-rail
DACs with integrated 10ppm/°C maximum reference . The
DACs have built-in high performance, rail-to-rail, output
buffers and are guaranteed monotonic. The LTC2654-L
has a full-scale output of 2.5V with the integrated refer-
ence and operates from a single 2.7V to 5.5V supply.
The LTC2654-H has a full-scale output of 4.096V with
the integrated reference and operates from a 4.5V to
5.5V supply. Each DAC can also operate with an external
reference, which sets the full-scale output to 2 times the
external reference voltage.
These DACs communicate via a SPI/MICROWIRE™ com-
patible 4-wire serial interface which operates at clock rates
up to 50MHz. The LTC2654 incorporates a power-on reset
circuit that is controlled by the PORSEL pin. If PORSEL
is tied to GND the DACs reset to zero-scale. If PORSEL is
tied to V_CC, the DACs reset to mid-scale.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. SPI/MICROWIRE is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5396245, 6891433 and patent pending.
BLOCK DIAGRAM
REFCOMP
GND
REFLO
V_OUTA
DAC A
INTERNAL REFERENCE
REFIN/OUT
V_CC
DAC D
V_OUTD
V_OUTB
DAC B
CS/LD
SCK
LDAC
CONTROL LOGIC
DECODE
32-BIT SHIFT REGISTER
DAC C
V_OUTC
POWER-ON
RESET
PORSEL
SDO
SDI
CLR
2654 TA01a
4
V_CC = 5V
3
INL Curve
2
1
0
–1
–2
–3
–4
128
16384
32768
CODE
49152 65535
2654 TA01b
2654f
1