LTC1742_15 Datasheet, PDF (1/20 Pages) Linear Technology – 14-Bit, 65Msps Low Noise ADC

FEATURES
s _{Sample Rate: 65Msps}
s _{76.5dB SNR and 90dB SFDR (3.2V Range)}
s _{72.8dB SNR and 90dB SFDR (2V Range)}
s _{No Missing Codes}
s _{Single 5V Supply}
s _{Power Dissipation: 1.275W}
s _{Selectable Input Ranges: ±1V or ±1.6V}
s _{240MHz Full Power Bandwidth S/H}
s _{Pin Compatible Family}
25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit)
50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit)
65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit)
80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)
s _{48-Pin TSSOP Package}
U
APPLICATIO S
s _{Telecommunications}
s _Receivers
s _{Cellular Base Stations}
s _{Spectrum Analysis}
s _{Imaging Systems}
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTC1742
14-Bit, 65Msps Low Noise ADC
DESCRIPTIO
The LTC^®1742 is an 65Msps, sampling 14-bit A/D con-
verter designed for digitizing high frequency, wide dy-
namic range signals. Pin selectable input ranges of ±1V
and ±1.6V along with a resistor programmable mode
allow the LTC1742’s input range to be optimized for a wide
variety of applications.
The LTC1742 is perfect for demanding communications
applications with AC performance that includes 76.5dB
SNR and 90dB spurious free dynamic range. Ultralow jitter
of 0.15ps_RMS allows undersampling of IF frequencies with
excellent noise performance. DC specs include ±3LSB INL
and ±1LSB DNL.
The digital interface is compatible with 5V, 3V, 2V and
LVDS logic levels. The ENC and ENC inputs may be driven
differentially from PECL, GTL and other low swing logic
families or from single-ended TTL or CMOS. The low
noise, high gain ENC and ENC inputs may also be driven
by a sinusoidal signal without degrading performance. A
separate output power supply can be operated from 0.5V
to 5V, making it easy to connect directly to low voltage
DSPs or FIFOs.
The TSSOP package with a flow-through pinout simplifies
the board layout.
BLOCK DIAGRA
A_IN+
±1V
DIFFERENTIAL
ANALOG INPUT _AIN–
SENSE
RANGE
SELECT
V_CM
4.7µF
2.35V_REF
65Msps, 14-Bit ADC with a 2V Differential Input Range
S/H
14-BIT
CORRECTION
LOGIC AND
14
OUTPUT
AMP
PIPELINED ADC
SHIFT
LATCHES
REGISTER
OV_DD
0.1µF
OF
•••
D13
D0
CLKOUT
OGND
0.5V
TO 5V
0.1µF
BUFFER
DIFF AMP
CONTROL LOGIC
V_DD
1µF
5V
1µF
1µF
GND
REFLB
0.1µF
1µF
REFHA
4.7µF
REFLA REFHB ENC ENC MSBINV
0.1µF _DIFFERENTIAL
1µF
ENCODE INPUT
1742 BD
OE
1742f
1