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LTC3851_15 Datasheet, PDF (22/28 Pages) Linear Technology – Synchronous Step-Down Switching Regulator Controller
LTC3851
APPLICATIONS INFORMATION
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3851. These items are also illustrated graphically
in the layout diagram of Figure 9. Check the following in
your layout:
1. Are the board signal and power grounds segregated?
The LTC3851 GND pin should tie to the ground plane
close to the input capacitor(s). The low current or signal
ground lines should make a single point tie directly to
the GND pin. The synchronous MOSFET source pins
should connect to the input capacitor(s) ground.
2. Does the VFB pin connect directly to the feedback resis-
tors? The resistive divider R1, R2 must be connected
between the (+) plate of COUT and signal ground. The
47pF to 100pF capacitor should be as close as possible
to the LTC3851. Be careful locating the feedback resis-
tors too far away from the LTC3851. The VFB line should
not be routed close to any other nodes with high slew
rates.
3. Are the SENSE– and SENSE+ leads routed together
with minimum PC trace spacing? The filter capaci-
tor between SENSE+ and SENSE– should be as close
as possible to the LTC3851. Ensure accurate current
sensing with Kelvin connections as shown in Figure
10. Series resistance can be added to the SENSE lines
to increase noise rejection and to compensate for the
ESL of RSENSE.
0.1μF
RFREQ
1
16
MODE/PLLIN SW
2
15
FREQ/PLLFLTR TG
CSS
RC CC
47pF
3
RUN
14
BOOST
LTC3851
4
TK/SS
13
VIN
CC2
5
ITH
12
INTVCC
6
VFB
11
BG
7 SENSE–
1000pF
10Ω
8 SENSE+
10Ω
10
GND
9
ILIM
CB
DB
+
4.7μF
R1
COUT
R2
+
M1
CIN
+
VIN
M2
L1
RSENSE
–
–
VOUT
+
3851 F09
Figure 9. LTC3851 Layout Diagram
3851fb
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