LTC3851_15 Datasheet, PDF (16/28 Pages) Linear Technology – Synchronous Step-Down Switching Regulator Controller

LTC3851
APPLICATIONS INFORMATION
V_MASTER
R3
TO
TK/SS
PIN
R4
V_OUT
R3
TO
V_FB
PIN
R4
V_MASTER
R1
TO
TK/SS
PIN
R2
V_OUT
R3
TO
V_FB
PIN
R4
(4a) Coincident Tracking Setup
3851 F04
(4b) Ratiometric Tracking Setup
Figure 4. Setup for Coincident and Ratiometric Tracking
TK/SS
0.8V
V_FB
I
I
+
D1 D2
EA
–
D3
3851 F05
Figure 5. Equivalent Input Circuit of Error Amplifier
mode, the TK/SS voltage is substantially higher than
0.8V at steady-state and effectively turns off D1. D2 and
D3 will therefore conduct the same current and offer
tight matching between V_FB and the internal precision
0.8V reference. In the ratiometric mode, however, TK/SS
equals 0.8V at steady-state. D1 will divert part of the bias
current to make V_FB slightly lower than 0.8V.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
of output voltage deviation. Furthermore, when the master
supply’s output experiences dynamic excursion (under
load transient, for example), the slave channel output will
be affected as well. For better output regulation, use the
coincident tracking mode instead of ratiometric.
INTV_CC Regulator
The LTC3851 features a PMOS low dropout linear regulator
(LDO) that supplies power to INTV_CC from the V_IN supply.
INTV_CC powers the gate drivers and much of the LTC3851 ’s
internal circuitry. The LDO regulates the voltage at the
INTV_CC pin to 5V.
The LDO can supply a peak current of 50mA and must
be bypassed to ground with a minimum of 2.2μF ceramic
capacitor or low ESR electrolytic capacitor. No matter
16
what type of bulk capacitor is used, an additional 0.1μF
ceramic capacitor placed directly adjacent to the INTV_CC
and GND pins is highly recommended. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3851 to be
exceeded. The INTV_CC current, which is dominated by the
gate charge current, is supplied by the 5V LDO.
Power dissipation for the IC in this case is highest and
is approximately equal to V_IN • I_INTVCC. The gate charge
current is dependent on operating frequency as discussed
in the Efficiency Considerations section. The junction
temperature can be estimated by using the equations given
in Note 3 of the Electrical Characteristics. For example,
the LTC3851 INTV_CC current is limited to less than 14mA
from a 36V supply in the GN package:
T_J = 70°C + (14mA)(36V)(110°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (MODE/PLLIN
= INTV_CC) at maximum V_IN.
Topside MOSFET Driver Supply (C_B, D_B)
An external bootstrap capacitor C_B connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFET. Capacitor C_B in the Functional Diagram is charged
though external diode D_B from INTV_CC when the SW pin
is low. When the topside MOSFET is to be turned on, the
driver places the C_B voltage across the gate source of the
MOSFET. This enhances the MOSFET and turns on the
topside switch. The switch node voltage, SW, rises to V_IN
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